Design of Low-Voltage High-Performance Sample and Hold Circuit in 0.18μm CMOS Technology

Over the last two decade, digital signal processing (DSP) has grown rapidly in electronic systems to provide more reconfigureability and programmability in the applications, compared to analog component, which allows easier design and test automation. Digital circuit usage is increasing because of scaling properties of very large scale integration (VLSI) processes. This has allowed new generation of digital circuit to attain higher speed, more functionality per chip, low power dissipation, lower cost. Analog world, analog to digital converter (ADC) are used to convert the signal from analog to digital domain. For interfacing with DSP sample and hold (S/H) circuit is a key building block in, and is often used in front end of the ADCs to relax their timing requirement. The function of S/H circuit is to take samples to its input signal and hold these samples in its output for some period of time. The analog circuits in low voltage and low power have assumed great significance due to mixed-mode design required for modern electronic gadgets that demand portability and little power consumption. The mixed mode circuit has existence of both analog and digital circuits on the same chip and it is possible to have low voltage digital circuit in modern scaled-down technologies. However the same is not always true with analog circuits due to the constrains of device noise level and threshold voltage (VT) of MOSFET. Thus for analog circuit to co-exist on the same substrate along with digital system and share same supply voltage, the operation of analog circuit in low voltage environment is essential. The objective of this research is to design a low-voltage, high-performance S/H circuit that will address the above problems. A typical switch capacitor S/H circuit needs amplifier, switches and capacitor. New amplifier have been designed by using the architecture of single stage fully differential folded cascode low voltage operation transconductance amplifier (OTA) which has high gain and speed; the gin boosting technique was used for purpose of increasing the gain of the OTA. This technique does not affect the speed of the single stage. The transmission gate switches using CMOS devices, which have higher linearity and higher speed over a single MOS switch, have been designed for use in the S/H circuit. The switches are operated by clock generator with two non overlapping clock signals having low rise and fall time offering low noise for the S/H circuit. The clock was designed with 77.17ps rise and fall time to reduce the errors of driving MOS switches which results in higher linearity. The S/H circuit was designed to operate with 1.8V supply voltage in 0.18um technology. The sampling rate is 40MSPS with spurious free dynamic range (SFDR) 65.7dB and SNR 70dB

A 12-bit, 40 msamples/s, low-power, low-area pipeline analog-to-digital converter in CMOS 0.18 mum technology.

With advancements in digital signal processing in recent years, the need for high-speed, high-resolution analog-to-digital converters (ADCs) which can be used in the analog front-end has been increasing. Some examples of these applications are image and video signal processing, wireless communications and asymmetrical digital subscriber line (ADSL). In CMOS integrated circuit design, it is desirable to integrate the digital circuit and the ADC in one microchip to reduce the cost of fabrication. Consequently the power dissipation and area of the ADCs are important design factors. The original contributions in this thesis are as follows. Since the performance of pipeline ADCs significantly depends on the op-amps and comparators circuits, the performance of various comparators is analyzed and the effect of op-amp topology on the performance of pipeline ADCs is investigated. This thesis also presents a novel architecture for design of low-power and low-area pipelined ADCs which will be more useful for very low voltage applications in the future. At the schematic level, a low-power CMOS implementation of the current-mode MDAC is presented and an improved voltage comparator is designed. With the proposed design and the optimization methodology it is possible to reduce power dissipation and area compared with conventional fully differential schemes.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .M64. Source: Masters Abstracts International, Volume: 43-01, page: 0281. Adviser: C. Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Phase Noise in CMOS Phase-Locked Loop Circuits

Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

Design techniques for low power mixed analog-digital circuits with application to smart wireless systems.

This dissertation presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology. The application domain of the devised techniques is radio frequency identification (RFID) systems, however the presented techniques are applicable to wide range of mixed mode analog-digital applications. Hence the techniques herein apply to a range of smart wireless or mobile systems. The integration of both analog and digital circuits on a single substrate has many benefits such as reducing the system power, increasing the system reliability, reducing the system size and providing high inter-system communications speed - hence, a cost effective system implementation with increased performance. On the other hand, some difficulties arise from the fact that standard low-cost CMOS technologies are tuned toward maximising digital circuit performance and increasing transistor density per unit area. Usually these technologies have a wide spread in transistor parameters that require new design techniques that provide circuit characteristics based on relative transistor parameters rather than on the absolute value of these parameters. This research has identified new design techniques for mostly analog and some digital circuits for implementation in standard CMOS technologies with design parameters dependent on the relative values of process parameters, resulting in technology independent circuit design techniques. The techniques presented and discussed in this dissertation are (i) applied to the design of low-voltage and low-power controlled gain amplifiers, (ii) digital trimming techniques for operational amplifiers, (iii) low-power and low-voltage Schmitt trigger circuits, (iv) very low frequency to medium frequency low power oscillators, (v) low power Gray code counters, (vi) analog circuits utilising the neuron MOS transistor, (vii) high value floating resistors, and (viii) low power application specific integrated circuits (ASICs) that are particularly needed in radio frequency identification systems. The new techniques are analysed, simulated and verified experimentally via five chips fabricated through the MOSIS service.Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 200

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

Robust high-accuracy high-speed continuous-time CMOS current comparator

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date