Low-voltage, high-gain, and high-mobility organic complementary inverters based on N,N'-ditridecyl-3,4,9,10-perylenetetracarboxylic diimide and pentacene

This is the pre-peer reviewed version of the following article: PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS 2(2): 47-49, 2008 FULL CITE, which has been published in final form at http://www3.interscience.wiley.com/journal/117862140/abstract.ArticlePHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS. 2(2): 47-49 (2008)journal articl

Network housekeeping with stretched low voltage limits

This paper looks into solutions a grid operator has to cope with, taking into account high penetration of high penetration of renewable sources and new loads in the LV grid. Next to that it answers the following main research questions: - what will happen when the low voltage limits will be stretched from ±10% (current value) to e.g. ±15% (with or without time limitation)? - what must a DSO do to realise such a change (technical, legal, ….)? To answer these questions a literature study, simulation, tests and extensive surveys amongst key stakeholders were performed. Finally, recommendations and alternatives are proposed towards the community of DSOs following EN50160

Millivolt signal limiter

Low-voltage limiter circuit suppresses the output of platinum probes at temperatures beyond their operating range. The limiter circuit comprises an operational amplifier with a dual feedback loop. The signal limiter is useful in low-voltage instrumentation circuits normally operable or set for cryogenic temperatures

Electric vehicles – effects on domestic low voltage networks

Electric Vehicles (EV) charging from a domestic power socket are becoming increasingly popular due to their economic and environmental benefits. The large number of such vehicles presents a significant additional load on existing low voltage (LV) power distribution networks (PDN). Evaluating this impact is essential for distribution network operators (DNO) to ensure normal functioning of the distribution grid. This research uses predictions of EV development and penetration levels to create a stochastic model of aggregate charging demand in a neighbourhood. Combined with historic distribution substations data from the Milton Keynes, UK total loads on the distribution transformers are projected. The results show significant overloading can occur with uncoordinated charging with just 25% of EVs on the road. The traditional way to solve this problem would be upgrading the transformer; however, that could be avoided by implementing coordinated charging to redistribute the load

Electron Multiplying Low-Voltage CCD With Increased Gain

Novel designs for the gain elements in electron multiplying (EM) CCDs have been implemented in a device manufactured in a low voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this work can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain ageing

Inverter-Based Low-Voltage CCII- Design and Its Filter Application

This paper presents a negative type second-generation current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCII- could be operated in a very low supply voltage such as ±0.5V. The proposed CCII- has wide input voltage range (±0.24V), wide output voltage (±0.24V) and wide output current range (±24mA). The proposed CCII- has no on-chip capacitors, so it can be designed with standard CMOS digital processes. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The proposed CCII- has been fabricated in TSMC 0.18μm CMOS processes and it occupies 1189.91 x 1178.43μm2 (include PADs). It can also be validated by low voltage CCII filters