Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

A CMOS Digital Beamforming Receiver

As the demand for high speed communication is increasing, emerging wireless techniques seek to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming provides multiple simultaneous beams without an SNR penalty, is more accurate, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, and the need for large numbers of analog-to-digital converters. Furthermore, beam squinting errors and ADC non-linearity limit the use of large digital beamforming arrays. We address these limitations. First, we address the power and area challenge by combining Interleaved Bit Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. Furthermore, the new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% compared to previous work. Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting. True-time-delay beamforming eliminates squinting, making it an ideal choice for large-array wide-bandwidth applications. Third, we present a new current-steering DAC architecture that provides a constant output impedance to improve ADC linearity. This significantly reduces distortion, leading to an SFDR improvement of 13.7 dB from the array. Finally, we provide analysis to show that the ADC power consumption of a digital beamformer is comparable to that of the ADC power for an analog beamformer. To summarize, we present a prototype phased array and a prototype timed array, both with 16 elements, 4 independent beams, a 1 GHz center frequency, and a 100 MHz bandwidth. Both the phased array and timed array achieve nearly ideal conventional and adaptive beam patterns, including beam tapering and adaptive nulling. With an 11.2 dB array gain, the phased array achieves a 58.5 dB SNDR over a 100 MHz bandwidth, while consuming 312 mW and occupying 0.22 mm2. The timed array achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512, occupies only 0.29 mm2, and consumes 453 mW.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147716/1/smjang_1.pd

Switched-Capacitor RF Receivers for High Interferer Tolerance

The demand for broadband wireless communication is growing rapidly, requiring more spectrum resources. However, spectrum usage is inefficient today because different frequency bands are allocated for different communication standards and most of the bands are not highly occupied. Cognitive radio systems with dynamic spectrum access improve spectrum efficiency, but they require wideband tunable receiver hardware. In such a system, a preselect filter is required for the RF receiver front end, because an out-of-band (OB) interferer can block the front end or cause distortion, desensitizing the receiver. In a conventional solution, off-chip passive filters, such as surface-acoustic-wave (SAW) filters, are used to reject the OB interferer. However, such passive filters are hardly tunable, have large area, and are very expensive. On-chip, high-selectivity, linearly tunable RF filters are, therefore, a hot topic in RF front-end research. Switched-capacitor (SC) RF filters, such as N-path filters, feature good linearity and tunability, making them good candidates for tunable RF filters. However, N-path filters have some drawbacks: notably, a poor harmonic response and limited close-by blocker tolerance. This thesis presents the design and implementation of several interferer-tolerant receivers based on SC technology. We present an RF receiver with a harmonic-rejecting N-path filter to improve the harmonic response of the N-path bandpass filter. It features tunable narrowband filtering and high attenuation of the third- and fifth-order LO harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2-1 GHz RF receiver is implemented in a 65 nm CMOS process. The blocker 1 dB compression point (B1dB) is -2.4 dBm at a 20 MHz offset, and remains high at the third- and fifth-order LO harmonics. The LNA’s reverse isolation helps keep the LO emission below -90 dBm. A two-stage harmonic-rejection approach offers a > 51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration. To improve tolerance for close-by blockers, we further present an SC RF receiver achieving high-order, tunable, highly linear RF filtering. We implement RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering and downconversion using only switches and capacitors in a 0.1-0.7 GHz prototype with tunable center frequency, programmable filter order, and very high tolerance for OB blockers. The 40 nm CMOS receiver consumes 38.5-76.5mA, achieves 40 dB gain, 24 dBm OB IIP3, 14.7 dBm B1dB for a 30MHz blocker offset, 6.8-9.7 dB noise figure, and > 66dB calibrated harmonic rejection ratio. The key drawback of our earlier SC receiver is the relatively high theoretical lower limit of the noise figure. To improve the noise performance, we developed a 0.1-0.6 GHz chopping SC RF receiver with an integrated blocker detector. We achieve RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping with passive SC circuits only. The 34-80 mW 65 nm receiver achieves 35 dB gain, 4.6-9 dB NF, 31 dBm OB-IIP3, and 15 dBm B1dB. The 0.2 mW integrated blocker detector detects large OB blockers with only a 1 us response time. The filter order can be adapted to blocker power with the blocker detector

Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog) domain into utilizing charge or time as the variable that can be processed by mostly digital/passive circuits. In this thesis, both circuit-level techniques and architectures are proposed that are inherently compatible with transistor scaling in submicron CMOS, meanwhile achieving state-of-the-art performance and optimizing power efficiency. The first part focuses on a highly reconfigurable charge-domain switched-g[subscript m]-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge sharing technique. It uses only switches, capacitors, linearity-enhanced gm-stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and -3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two proposed biquads in a 65nm LPE CMOS process. A tunable center frequency of 35−70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies a core area of 0.17mm². In the second part, a highly linear continuous-time low-pass filter (LPF) topology with source follower coupling is presented that achieves excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two proposed filter stages in a 0.18μm CMOS, and occupies a core area of 0.12mm². Operating with a 1.3V supply voltage, the filter consumes only 0.5mA current, and achieves a -3dB bandwidth of 20MHz with 82dB stop-band rejection. A total harmonic distortion (THD) of -39.5dB at the output is measured with a +6.6dBm (i.e. 1.35V[subscript pk-pk]) input signal at 2MHz. The measured in-band IIP3 is +28.8dBm. The dynamic range (at 1% THD) is 76.8dB, with 15.3nV/√Hz averaged in-band input-referred noise. A pseudo-differential-VCO based 2nd-order continuous-time ΔΣ ADC with a residue self-coupling technique is proposed and implemented with mostly digital circuits in the third part. Two VCOs are arranged in a pseudo-differential manner. The digital output is obtained by comparing the sampled output phase of one VCO with that of the other. Passive subtraction is realized in current domain to obtain the residue at the VCO input. The residue self-coupling is implemented using a linear 1st-order transconductance low-pass filter (TCLPF). Moreover, a highly linear VCO topology is presented. The transistor-level simulations in a 65nm CMOS process show a 78dB SNDR over a 10MHz signal bandwidth with a power consumption of 2.9mW, which is 16dB improvement in contrast to the case with the TCLPF block powered off

Compressive Sampling as an Enabling Solution for Energy-Efficient and Rapid Wideband RF Spectrum Sensing in Emerging Cognitive Radio Systems

Wireless systems have become an essential part of every sector of the national and global economy. In addition to existing commercial systems including GPS, mobile cellular, and WiFi communications, emerging systems like video over wireless, the Internet of Things, and machine-to-machine communications are expected to increase mobile wireless data traffic by several orders of magnitude over the coming decades, while natural resources like energy and radio spectrum remain scarce. The projected growth of the number of connected nodes into the trillions in the near term and increasing user demand for instantaneous, over-the-air access to large volumes of content will require a 1000-fold increase in network wireless data capacity by 2020. Spectrum is the lifeblood of these future wireless networks and the ’data storm’ driven by emerging technologies will lead to a pressing ’artificial’ spectrum scarcity. Cognitive radio is a paradigm proposed to overcome the existing challenge of underutilized spectrum. Emerging cognitive radio systems employing multi-tiered, shared-spectrum access are expected to deliver superior spectrum efficiency over existing scheduled-access systems; they have several device categories (3 or more tiers) with different access privileges. We focus on lower tiered ’smart’ devices that evaluate the spectrum dynamically and opportunistically use the underutilized spectrum. These ’smart’ devices require spectrum sensing for incumbent detection and interferer avoidance. Incumbent detection will rely on database lookup or narrowband high-sensitivity sensing. Integrated interferer detectors, on the other hand, need to be fast, wideband, and energy efficient, while requiring only moderate sensitivity. These future 'smart' devices operating in small cell environments will need to rapidly (in 10s of μs) detect a few (e.g. 3 to 6) strong interferers within roughly a 1GHz span and accordingly reconfigure their hardware resources or request adjustments to their wireless connection consisting of primary and secondary links in licensed and unlicensed spectrum. Compressive sampling (CS), an evolutionary sensing/sampling paradigm that changes the perception of sampling, has been extensively used for image reconstruction. It has been shown that a single pixel camera that exploits CS has the ability to obtain an image with a single detection element, while measuring the image fewer times than the number of pixels with the prior assumption of sparsity. We exploited CS in the presented works to take a ’snapshot’ of the spectrum with low energy consumption and high frequency resolutions. Compressive sampling is applied to break the fixed trade-off between scan time, resolution bandwidth, hardware complexity, and energy consumption. This contrasts with traditional spectrum scanning solutions, which have constant energy consumption in all architectures to first order and a fixed trade-off between scan time and resolution bandwidth. Compressive sampling enables energy-efficient, rapid, and wideband spectrum sensing with high frequency resolutions at the expense of degraded instantaneous dynamic range due to the noise folding. We have developed a quadrature analog-to-information converter (QAIC), a novel CS rapid spectrum sensing technique for band-pass signals. Our first wideband, energy-efficient, and rapid interferer detector end-to-end system with a QAIC senses a wideband 1GHz span with a 20MHz resolution bandwidth and successfully detects up to 3 interferers in 4.4μs. The QAIC offers 50x faster scan time compared to traditional sweeping spectrum scanners and 6.3x the compressed aggregate sampling rate of traditional concurrent Nyquist-rate approaches. The QAIC is estimated to be two orders of magnitude more energy efficient than traditional spectrum scanners/sensors and one order of magnitude more energy efficient than existing low-pass CS spectrum sensors. We implemented a CS time-segmented quadrature analog-to-information converter (TS-QAIC) that extends the physical hardware through time segmentation (e.g. 8 physical I/Q branches to 16 I/Q through time segmentation) and employs adaptive thresholding to react to the signal conditions without additional silicon cost and complexity. The TS-QAIC rapidly detects up to 6 interferers in the PCAST spectrum between 2.7 and 3.7GHz with a 10.4μs sensing time for a 20MHz RBW with only 8 physical I/Q branches while consuming 81.2mW from a 1.2V supply. The presented rapid sensing approaches enable system scaling in multiple dimensions such as ADC bits, the number of samples, and the number of branches to meet user performance goals (e.g. the number of detectable interferers, energy consumption, sensitivity and scan time). We envision that compressive sampling opens promising avenues towards energy-efficient and rapid sensing architectures for future cognitive radio systems utilizing multi-tiered, shared spectrum access

Proceedings of the 35th WIC Symposium on Information Theory in the Benelux and the 4th joint WIC/IEEE Symposium on Information Theory and Signal Processing in the Benelux, Eindhoven, the Netherlands May 12-13, 2014

Compressive sensing (CS) as an approach for data acquisition has recently received much attention. In CS, the signal recovery problem from the observed data requires the solution of a sparse vector from an underdetermined system of equations. The underlying sparse signal recovery problem is quite general with many applications and is the focus of this talk. The main emphasis will be on Bayesian approaches for sparse signal recovery. We will examine sparse priors such as the super-Gaussian and student-t priors and appropriate MAP estimation methods. In particular, re-weighted l2 and re-weighted l1 methods developed to solve the optimization problem will be discussed. The talk will also examine a hierarchical Bayesian framework and then study in detail an empirical Bayesian method, the Sparse Bayesian Learning (SBL) method. If time permits, we will also discuss Bayesian methods for sparse recovery problems with structure; Intra-vector correlation in the context of the block sparse model and inter-vector correlation in the context of the multiple measurement vector problem

Computadora de vuelo para adquisición de datos cinemáticos en tiempo real en micro aeronaves

En los Vehículos Aéreos No Tripulados (VANTs), es necesario contar con un sistema de cómputo, comúnmente llamado Computadora de Vuelo (CV), que se encargue de la obtención, procesamiento y almacenamiento de datos de aire, datos inerciales, datos de navegación por estimación y datos de posicionamiento. Además de lo anterior, la computadora de vuelo debe contar con algoritmos que le permitan actuar sobre las superficies de control de la aeronave para garantizar su correcto funcionamiento sobre un amplio rango de situaciones, a este subsistema se le conoce como Autopiloto [1]. En este trabajo se plantea la construcción y prueba de una CV para VANTs, en particular, se aborda el problema mediante la integración de hardware comercial (COTS - Commercial Off-The-Shelf) con algoritmos de obtención, procesamiento, almacenamiento y control propios