Advances on CMOS image sensors

This paper offers an introduction to the technological advances of image sensors designed using complementary metal–oxide–semiconductor (CMOS) processes along the last decades. We review some of those technological advances and examine potential disruptive growth directions for CMOS image sensors and proposed ways to achieve them. Those advances include breakthroughs on image quality such as resolution, capture speed, light sensitivity and color detection and advances on the computational imaging. The current trend is to push the innovation efforts even further as the market requires higher resolution, higher speed, lower power consumption and, mainly, lower cost sensors. Although CMOS image sensors are currently used in several different applications from consumer to defense to medical diagnosis, product differentiation is becoming both a requirement and a difficult goal for any image sensor manufacturer. The unique properties of CMOS process allows the integration of several signal processing techniques and are driving the impressive advancement of the computational imaging. With this paper, we offer a very comprehensive review of methods, techniques, designs and fabrication of CMOS image sensors that have impacted or might will impact the images sensor applications and markets

Ultralow-power processing array for image enhancement and edge detection

This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be turned into anisotropic by a very simple voltage comparator between neighboring nodes whose output controls the gate of the elementary MOS resistor. Anisotropic diffusion enables image enhancement by removing noise and small local variations while preserving edges. A binary edge image can also be attained by combining the output of the voltage comparators. In addition to these processing capabilities, the simulations have confirmed the robustness of the array against process variations and mismatch. The power consumption extrapolated for VGA-resolution array processing images at 30 fps is 570 μW

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

A Low-Power Capacitive Transimpedance D/A Converter

This thesis proposes a new low-power and low-area DAC for single-slope ADCs used in CMOS image sensors. With increase in resolution requirements for ADCs, conventional DAC architectures suffered the limitation of either large area or high power consumption with higher resolution scaling. Thus, the proposed capacitive transimpedance amplifier DAC (CTIA DAC) could solve this by offering the resolution requirement required without taking a hit on the area or power budget. The thesis has been structured in the following manner: The first chapter introduces image sensors in general and talks about progression through different image sensors and pixel architectures that have been used through the years. It also explains the operation of a CMOS image sensor from a paper published from Sony on high-speed image sensors. The second chapter presents the importance and role of DACs in CMOS image sensors and briefly explains a few commonly used DAC architectures in image sensors. It explains the advantages and disadvantages of present architectures and leads the discussion towards the development of the proposed DAC. The third chapter gives an overview of the CTIA DAC and explains the working of the different circuit blocks that are used to implement the proposed DAC. Chapter Four explains the design approach for the blocks explained in Chapter Three. It presents the critical design choices that were made for overall performance of the DAC. Results of individual blocks and the DAC as a whole are presented and compared against other recently published DAC papers. The final chapter summarizes some key results of the design and talks about the scope for future work and improvement

Space optical instruments optimisation thanks to CMOS image sensor technology

Today, both CCD and CMOS sensors can be envisaged for nearly all visible sensors and instruments designed for space needs. Indeed, detectors built with both technologies allow excellent electro-optics performances to be reached, the selection of the most adequate device being driven by their functional and technological features and limits. The first part of the paper presents electro-optics characterisation results of CMOS Image Sensors (CIS) built with an optimised CMOS process, demonstrating the large improvements of CIS electro-optics performances. The second part reviews the advantages of CMOS technology for space applications, illustrated by examples of CIS developments performed by EADS Astrium and Supaéro/CIMI for current and short term coming space programs

Form Factor Improvement of Smart-Pixels for Vision Sensors through 3-D Vertically- Integrated Technologies

While conventional CMOS active pixel sensors embed only the circuitry required for photo-detection, pixel addressing and voltage buffering, smart pixels incorporate also circuitry for data processing, data storage and control of data interchange. This additional circuitry enables data processing be realized concurrently with the acquisition of images which is instrumental to reduce the number of data needed to carry to information contained into images. This way, more efficient vision systems can be built at the cost of larger pixel pitch. Vertically-integrated 3D technologies enable to keep the advnatges of smart pixels while improving the form factor of smart pixels.Office of Naval Research N000141110312Ministerio de Ciencia e Innovación IPT-2011-1625-43000

Smart Sensor Networks For Sensor-Neural Interface

One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface. In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5μm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18μm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system. The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access