Built-in-self-test and foreground calibration of SAR ADCs

This thesis explores the scope of ‘Built-in-Self-Test’(BIST) schemes to reduce the time cost complexity associated with the production tests for static linearity errors in Successive Approximation (SAR) ADCs. In this regard, an on-chip implementation of the ‘Stimulus Based Error Identification and Removal’ (SEIR) method [1] is sought to be pursued. As an extension, it is proposed that the estimated ADC non-linearities may then be suitably calibrated to achieve higher resolution. A brief review of the testing and calibration algorithm is undertaken. Further, this work elaborates on the design of a prototype front-end test generator and a buffer interface to calibrate a 10MHz 14 bit redundant SAR ADC in the TSMC 180nm process. Simulation results validating the circuit implementation of the integrated front-end system have been presented.Electrical and Computer Engineerin

Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters

The evaluation of the linearity performance of a high resolution Analog-to- Digital Converter (ADC) by the Standard Histogram method is an outstanding challenge due to the requirement of high purity of the input signal and the high number of output data that must be acquired to obtain an acceptable accuracy on the estimation. These requirements become major application drawbacks when the measures have to be performed multiple times within long test flows and for many parts, and under an industrial environment that seeks to reduce costs and lead times as is the case in the New Space sector. This thesis introduces two alternative methods that succeed in relaxing the two previous requirements for the estimation of the Integral Nonlinearity (INL) parameter in ADCs. The methods have been evaluated by estimating the Integral Non-Linearity pattern by simulation using realistic high-resolution ADC models and experimentally by applying them to real high performance ADCs. First, the challenge of applying the Standard Histogram method for the evaluation of static parameters in high resolution ADCs and how the drawbacks are accentuated in the New Space industry is analysed, being a highly expensive method for an industrial environment where cost and lead time reduction is demanded. Several alternative methods to the Standard Histogram for estimating Integral Nonlinearity in high resolution ADCs are reviewed and studied. As the number of existing works in the literature is very large and addressing all of them is a challenge in itself, only those most relevant to the development of this thesis have been included. Methods based on spectral processing to reduce the number of data acquired for the linearity test and methods based on a double histogram to be able to use generators that do not meet the the purity requirement against the ADC to be tested are further analysed. Two novel contributions are presented in this work for the estimation of the Integral Nonlinearity in ADCs, as possible alternatives to the Standard Histogram method. The first method, referred to as SSA (Simple Spectral Approach), seeks to reduce the number of output data that need to be acquired and focuses on INL estimation using an algorithm based on processing the spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard Histogram method, although the estimation accuracy will depend on how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm cannot be used to perform a calibration of the ADC nonlinearity error, but it can be applied to find out between which limits it lies and what its approximate shape is. The second method, named SDH (Simplified Double Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity generator. The approach uses two histograms constructed from the two set of output data in response to two identical input signals except for a dc offset between them. Using a simple adder model, an extended approach named ESDH (Extended Simplified Double Histogram) addresses and corrects for possible time drifts during the two data acquisitions, so that it can be successfully applied in a non-stationary test environment. According to the experimental results obtained, the proposed algorithm achieves high estimation accuracy. Both contributions have been successfully tested in high-resolution ADCs with both simulated and real laboratory experiments, the latter using a commercial ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital (ADC) de alta resolución mediante el método estándar del Histograma constituye un gran desafío debido los requisitos de alta pureza de la señal de entrada y del elevado número de datos de salida que deben adquirirse para obtener una precisión aceptable en la estimación. Estos requisitos encuentran importantes inconvenientes para su aplicación cuando las medidas deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un gran número de piezas, y todo bajo un entorno industrial que busca reducir costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos anteriores para la estimación de los parámetros de no linealidad en los ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad Integral (INL) mediante simulación utilizando modelos realistas de ADC de alta resolución y experimentalmente aplicándolos en ADCs reales. Inicialmente se analiza el reto que supone la aplicación del método estándar del Histograma para la evaluación de los parámetros estáticos en ADCs de alta resolución y cómo sus inconvenientes se acentúan en la industria del Nuevo Espacio, siendo un método altamente costoso para un entorno industrial donde se exige la reducción de costes y plazos de entrega. Se estudian métodos alternativos al Histograma estándar para la estimación de la No Linealidad Integral en ADCs de alta resolución. Como el número de trabajos es muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número de datos que necesitan ser adquiridos y los métodos basados en un doble histograma para poder utilizar generadores que no cumplen el requisito de precisión frente al ADC a medir. En este trabajo se presentan dos novedosas aportaciones para la estimación de la No Linealidad Integral en ADCs, como posibles alternativas al método estándar del Histograma. El primer método, denominado SSA (Simple Spectral Approach), busca reducir el número de datos de salida que es necesario adquirir y se centra en la estimación de la INL mediante un algoritmo basado en el procesamiento del espectro de la señal de salida cuando se utiliza un estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número mucho menor de muestras que el método estándar del Histograma, aunque la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón de no-linealidad del ADC a medir. En general, este algoritmo no puede utilizarse para realizar una calibración del error de no linealidad del ADC, pero puede aplicarse para averiguar entre qué límites se encuentra y cuál es su forma aproximada. El segundo método, denominado SDH (Simplified Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando un generador de baja pureza. El algoritmo utiliza dos histogramas, construidos a partir de dos conjuntos de datos de salida en respuesta a dos señales de entrada idénticas, excepto por un desplazamiento constante entre ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado ESDH (Extended Simplified Double Histogram) aborda y corrige las posibles derivas temporales durante las dos adquisiciones de datos, de modo que puede aplicarse con éxito en un entorno de prueba no estacionario. De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto alcanza una alta precisión de estimación. Ambas contribuciones han sido probadas en ADCs de alta resolución con experimentos tanto simulados como reales en laboratorio, estos últimos utilizando un ADC comercial con una resolución de 14 bits y una tasa de muestreo de 65Msps (AD6644 de Analog Devices)

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Delta STATCOM with partially rated energy storage for intended provision of ancillary services

This thesis presents research on two distinct areas, where the work carried out in the first half highlights the challenges posed by the declining system inertia in the future power systems and the potential capability of the energy storage systems in bridging the gap, supporting a safe and reliable operation. A comparison of various energy storage technologies based on their specific energy, specific power, response time, life-cycle, efficiency, cost and further correlating these characteristics to the timescale requirements of frequency and RoCoF services showed that supercapacitors (SC) and Li-ion batteries present the most suitable candidates. Results of a network stability study showed that for a power system rated at 2940 MVA with a high RES contribution of 1688 MVA, equating to 57% of the energy mix, during a power imbalance of 200 MW, an ESS designed to provide emulated inertia response (EIR) in isolation required a power and energy rating of 39.54 MW and 0.0365 MWh respectively. Similarly, providing primary frequency response (PFR) on its own required a power and energy rating of 114.52 MW and 2.14 MWh respectively. ESS providing these services in isolation was not able to maintain all the frequency operating limits and similar results were also seen in the case of the recently introduced Dynamic Containment service. However, with the introduction of a combined response capability, a significantly improved performance, comparable to that of the synchronous generators was observed. In order to maintain the RoCoF and the statutory frequency limit of 0.5 Hz/s and ±0.5 Hz respectively, an ESS must be able to respond with a delay time of no more than 0.2 seconds and be able to ramp up to full response within 0.3 seconds (0.5 seconds from the start of contingency) for a frequency deviation of ±0.5 Hz. The second half of the thesis focused on investigating the current state-of-the-art power conversion system topologies, with the objective of identifying a suitable topology for interfacing ESSs to the grid at MV level. A delta-connected Modular Multilevel STATCOM with partially rated storage (PRS-STATCOM) is proposed, capable of providing both reactive and active power support. The purpose is to provide short-term energy storage enabled grid support services such as inertial and frequency response, either alongside or temporarily instead of standard STATCOM voltage support. The topology proposed here contains two types of sub-modules (SM) in each phase-leg: standard sub-modules (STD-SMs) and energy storage element sub-modules (ESE-SMs) with a DC-DC interface converter between the SM capacitor and the ESE. A control structure has been developed that allows energy transfer between the SM capacitor and the ESE, resulting in an active power exchange between the converter and the grid. A 3rd harmonic current injection into the converter waveforms was used to increase the amount of power that can be extracted from the ESE-SMs and so reduce the required ESE-SMs fraction in each phase-leg. Simulation results demonstrate that for three selected active power ratings, 1 pu, 2/3 pu, & 1/3 pu, the fraction of SMs that need to be converted to ESE-SMs are only 69%, 59% & 38%. Thus, the proposed topology is effective in adding real power capability to a STATCOM without a large increase in equipment cost. Furthermore, modifying the initially proposed topology with the use of Silicon Carbide (SiC) switching devices and interleaved DC-DC interface converter with inverse coupled inductors resulted in similar efficiencies when operated in STATCOM mode.Open Acces

Hybrid Energy Storage Implementation in DC and AC Power System for Efficiency, Power Quality and Reliability Improvements

Battery storage devices have been widely utilized for different applications. However, for high power applications, battery storage systems come with several challenges, such as the thermal issue, low power density, low life span and high cost. Compared with batteries, supercapacitors have a lower energy density but their power density is very high, and they offer higher cyclic life and efficiency even during fast charge and discharge processes. In this dissertation, new techniques for the control and energy management of the hybrid battery-supercapacitor storage system are developed to improve the performance of the system in terms of efficiency, power quality and reliability. To evaluate the findings of this dissertation, a laboratory-scale DC microgrid system is designed and implemented. The developed microgrid utilizes a hybrid lead-acid battery and supercapacitor energy storage system and is loaded under various grid conditions. The developed microgrid has also real-time monitoring, control and energy management capabilities. A new control scheme and real-time energy management algorithm for an actively controlled hybrid DC microgrid is developed to reduce the adverse impacts of pulsed power loads. The developed control scheme is an adaptive current-voltage controller that is based on the moving average measurement technique and an adaptive proportional compensator. Unlike conventional energy control methods, the developed controller has the advantages of controlling both current and voltage of the system. This development is experimentally tested and verified. The results show significant improvements achieved in terms of enhancing the system efficiency, reducing the AC grid voltage drop and mitigating frequency fluctuation. Moreover, a novel event-based protection scheme for a multi-terminal DC power system has been developed and evaluated. In this technique, fault identification and classifications are performed based on the current derivative method and employing an artificial inductive line impedance. The developed scheme does not require high speed communication and synchronization and it transfers much less data when compared with the traditional method such as the differential protection approach. Moreover, this scheme utilizes less measurement equipment since only the DC bus data is required

Integrated Water Resources Management Karlsruhe 2010 : IWRM, International Conference, 24 - 25 November 2010 conference proceedings

In dieser Arbeit werden dual-orthogonal, linear polarisierte Antennen für die UWB-Technik konzipiert. Das Prinzip zur Realisierung der Strahler wird vorgestellt, theoretisch und simulativ untersucht, sowie messtechnisch verifiziert. Danach werden Konzepte zur Miniaturisierung der Strahler dargelegt, die anschließend zum Aufbau von Antennengruppen verwendet werden. Die Vorteile der entwickelten Antennen werden praktisch anhand des bildgebenden Radars und des Monopuls-Radars gezeigt