CMOS RF front-end design for terrestrial and mobile digital television systems

With the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system; it down-converts the desired DTV RF channel to baseband or a low intermediate frequency with enough quality. This research is mainly focused on the analysis and realization of low-cost low-power front-ends for ATSC terrestrial DTV and DVB-H mobile DTV tuner systems. For the design of the ATSC terrestrial tuner, a novel double quadrature tuner architecture, which can not only minimize the tuner power consumption but also achieve the fully integration, has been proposed. A double quadrature down-converter has been designed and fabricated with TSMC 0.35õm CMOS technology; the measurement results verified the proposed concepts. For the mobile DTV tuner, a zero-IF architecture is used and it can achieve the DVB-H specifications with less than 200mW power consumption. In the implementation of the mobile DVB-H tuner, a novel RF variable gain amplifier (RFVGA) and a low flicker noise current-mode passive mixer have been proposed. The proposed RFVGA achieves high dynamic range and robust input impedance matching performance, which is the main design challenge for the traditional implementations. The current-mode passive mixer achieves high-gain, low noise (especially low flicker noise) and high-linearity (over 10dBm IIP3) with low power supplies; it is believed that this is a promising topology for low voltage high dynamic range mixer applications. The RFVGA has been fabricated in TSMC 0.18õm CMOS technology and the measurement results agree well with the theoretical ones

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re[CA] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor IRodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967TESI

High definition systems in Japan

The successful implementation of a strategy to produce high-definition systems within the Japanese economy will favorably affect the fundamental competitiveness of Japan relative to the rest of the world. The development of an infrastructure necessary to support high-definition products and systems in that country involves major commitments of engineering resources, plants and equipment, educational programs and funding. The results of these efforts appear to affect virtually every aspect of the Japanese industrial complex. The results of assessments of the current progress of Japan toward the development of high-definition products and systems are presented. The assessments are based on the findings of a panel of U.S. experts made up of individuals from U.S. academia and industry, and derived from a study of the Japanese literature combined with visits to the primary relevant industrial laboratories and development agencies in Japan. Specific coverage includes an evaluation of progress in R&D for high-definition television (HDTV) displays that are evolving in Japan; high-definition standards and equipment development; Japanese intentions for the use of HDTV; economic evaluation of Japan's public policy initiatives in support of high-definition systems; management analysis of Japan's strategy of leverage with respect to high-definition products and systems

Analog Baseband Filters and Mixed Signal Circuits for Broadband Receiver Systems

Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems. The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation). High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented. Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers. The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology

Conception et optimisation d'architectures radiofréquences pour la réjection de la fréquence image (applications aux systèmes de radiocommunications et liaisons de proximité)

Le développement de la radiocommunication sans fil et notamment, son explosion sur le marché grand public, a été rendu possible grâce au progrès du secteur de la microélectronique. En effet, l intégration toujours croissante de fonctions au sein d une même puce a permis le développement de ces nouvelles technologies basses consommations et à un moindre coût. Les travaux de recherche présentés dans ce manuscrit s inscrivent dans le cadre de ces deux caractéristiques (faible coût et faible consommation). Nous avons donc développé deux solutions innovantes d architectures radiofréquences : half-complex et full-complex en technologie CMOS. En effet, cette technologie représente la meilleure alternative car elle permet l implémentation de fonctions RF analogique et numérique sur une même puce réduisant ainsi le coût du système.Le développement de la radiocommunication sans fil et notamment, son explosion sur le marché grand public, a été rendu possible grâce au progrès du secteur de la microélectronique. En effet, l intégration toujours croissante de fonctions au sein d une même puce a permis le développement de ces nouvelles technologies basses consommations et à un moindre coût. Les travaux de recherche présentés dans ce manuscrit s inscrivent dans le cadre de ces deux caractéristiques (faible coût et faible consommation). Nous avons donc développé deux solutions innovantes d architectures radiofréquences : half-complex et full-complex en technologie CMOS. En effet, cette technologie représente la meilleure alternative car elle permet l implémentation de fonctions RF analogique et numérique sur une même puce réduisant ainsi le coût du système.AIX-MARSEILLE1-Bib.electronique (130559902) / SudocSudocFranceF

Design of multi-channel radio-frequency front-end for 200mhz parallel magnetic resonance imaging

The increasing demands for improving magnetic resonance imaging (MRI) quality, especially reducing the imaging time have been driving the channel number of parallel magnetic resonance imaging (Parallel MRI) to increase. When the channel number increases to 64 or even 128, the traditional method of stacking the same number of radio-frequency (RF) receivers with very low level of integration becomes expensive and cumbersome. However, the cost, size, power consumption of the Parallel MRI receivers can be dramatically reduced by designing a whole receiver front-end even multiple receiver front-ends on a single chip using CMOS technology, and multiplexing the output signal of each receiver front-end into one channel so that as much hardware resource can be shared by as many channels as possible, especially the digitizer. The main object of this research is focused on the analysis and design of fully integrated multi-channel RF receiver and multiplexing technology. First, different architectures of RF receiver and different multiplexing method are analyzed. After comparing the advantages and the disadvantages of these architectures, an architecture of receiver front-end which is most suitable for fully on-chip multi-channel design is proposed and a multiplexing method is selected. According to this proposed architecture, a four-channel receiver front-end was designed and fabricated using TSMC 0.18μm technology on a single chip and methods of testing in the MRI system using parallel planar coil array and phase coil array respectively as target coils were presented. Each channel of the receiver front-end includes an ultra low noise amplifier (LNA), a quadrature image rejection down-converter, a buffer, and a low-pass filter (LPF) which also acts as a variable gain amplifier (VGA). The quadrature image rejection downconverter consists of a quadrature generator, a passive mixer with a transimpedance amplifier which converts the output current signal of the passive mixer into voltage signal while acts as a LPF, and a polyphase filter after the TIA. The receiver has an over NF of 0.935dB, variable gain from about 80dB to 90dB, power consumption of 30.8mW, and chip area of 6mm2. Next, a prototype of 4-channel RF receiver with Time Domain Multiplexing (TDM) on a single printed circuit board (PCB) was designed and bench-tested. Then Parallel MRI experiment was carried out and images were acquired using this prototype. The testing results verify the proposed concepts

D21.3 Analysis of initial results at EuWIN@CTTC

Deliverable D21.3 del projecte europeu NEWCOM#The nature of this Deliverable of WP2.1 (“Radio interfaces for next-generation wireless systems”) is mainly descriptive and its purpose is to provide a report on the status of the different Joint Research Activities (JRAs) currently ongoing, some of them being performed on the facilities that are available at EuWInPeer ReviewedPreprin

Test estructural i predictiu per a circuits RF CMOS

En aquesta tesi s’ha desenvolupat una tècnica de test que permet testar un LNA i un mesclador, situats en el capçal RF d’un receptor CMOS, en una configuració de test semblant al mode normal de funcionament. La circuiteria necessària per a implementar aquesta tècnica consta d’un generador IF, per a generar el senyal IF de test, i d’un mesclador auxiliar, per a obtenir el senyal RF de test. Les observables de test escollides han estat l’amplitud de la tensió de sortida del mesclador i el component DC del corrent de consum. S’ha estudiat l’eficàcia de la tècnica de test proposada utilitzant les estratègies de test estructural i predictiu, mitjançant simulacions i mesures experimentals. La seva eficàcia és comparable a altres tècniques de test existents, però l’àrea addicional dedicada a la circuiteria test és inferior.En esta tesis se ha desarrollado una técnica de test que permite verificar un LNA y un mezclador, situados en el cabezal RF de un receptor CMOS, en una configuración de test similar al modo normal de funcionamiento. Los circuitos necesarios para implementar esta técnica son: un generador IF, que permite generar la señal IF de test, y un mezclador auxiliar, para obtener la señal RF de test. Las observables de test seleccionadas han sido la amplitud de la tensión de salida y la componente DC de la corriente de consumo. Se ha estudiado la eficacia de la técnica propuesta usando las estrategias de test estructural y predictiva, mediante simulaciones y medidas experimentales. Su eficacia es comparable a otras técnicas existentes, pero el área dedicada a la circuiteria de test es inferior.This PhD thesis develops a test technique intended for the RF front end of CMOS integrated receivers. This test technique allows testing individually the building blocks of the receiver in a sequential way. The test mode configuration of each block is similar to the normal mode operation. The auxiliary circuitry required to generate the test stimuli consists of an IF generator, which generates the IF test signal, and an auxiliary mixer that produces the RF test signal by mixing the IF test signal with the local oscillator signal. The test observables selected for the test are the voltage amplitude after the IF amplifier, and the DC component of the supply current in each block. The capability of the proposed test technique to perform structural and predictive test strategies has been validated by simulation and experimentally. Its efficiency is comparable to other existing techniques, but the silicon area overhead is lower