Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

ハードウェアリソースの高稼働率化に基づく細粒度多値リコンフィギャラブルVLSIアーキテクチャ

Tohoku University亀山充隆課

Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

Fully source-coupled logic based multiple-valued VLSI

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

Dual-rail multiple-valued current-mode VLSI with biasing current sources

科研費報告書収録論文(課題番号:12480064・基盤研究(B)(2) ・H12～H14/研究代表者:亀山, 充隆/配線ボトルネックフリー2線式多値ディジタルコンピューティングVLSIシステム

High-performance long NoC link using delay-insensitive current-mode signaling

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes.We presented novel implementation of high-performance long-range NoC link based onmultilevel current-mode signaling and delayinsensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantlycompared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8mm wire length is 1.222GWord/swhich is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10mm wire length its power consumption is 0.75mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.</p

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

自律電源電圧制御に基づく低消費電力リコンフィギャラブルVLSI アーキテクチャに関する研究

Tohoku University亀山充隆課