Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

Multi-Gigabit Wireless data transfer at 60 GHz

In this paper we describe the status of the first prototype of the 60 GHz wireless Multi-gigabit data transfer topology currently under development at University of Heidelberg using IBM 130 nm SiGe HBT BiCMOS technology. The 60 GHz band is very suitable for high data rate and short distance applications as for example needed in the HEP experments. The wireless transceiver consist of a transmitter and a receiver. The transmitter includes an On-Off Keying (OOK) modulator, an Local Oscillator (LO), a Power Amplifier (PA) and a BandPass Filter (BPF). The receiver part is composed of a BandPass- Filter (BPF), a Low Noise Amplifier (LNA), a double balanced down-convert Gilbert mixer, a Local Oscillator (LO), then a BPF to remove the mixer introduced noise, an Intermediate Amplifier (IF), an On-Off Keying demodulator and a limiting amplifier. The first prototype would be able to handle a data-rate of about 3.5 Gbps over a link distance of 1 m. The first simulations of the LNA show that a Noise Figure (NF) of 5 dB, a power gain of 21 dB at 60 GHz with a 3 dB bandwidth of more than 20 GHz with a power consumption 11 mW are achieved. Simulations of the PA show an output referred compression point P1dB of 19.7 dB at 60 GHz.Comment: Proceedings of the WIT201

Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

A 24-GHz SiGe Phased-Array Receiver—LO Phase-Shifting Approach

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 [degrees] for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB

Transformer based front-end for a low power 2.4 GHz transceiver

A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ω antenna impedance to almost 1 kΩ and so facilitates a low power transmitter and receiver. The simulated post-layout output power of the differential class-E power amplifier is 2.0 dBm with a drain efficiency of 28.4%. The direct-conversion receiver achieves a very low power consumption of 420 μW and a noise figure of 15.0 dB.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

A novel tuning technique for distributed voltage controlled oscillators

A novel current-steering delay-balanced tuning technique for distributed voltage controlled oscillators (DVCO) is demonstrated. This tuning technique is used to design a DVCO operating at 10 GHz in a 0.35 μm CMOS technology. The DVCO is continuously tunable between 9.9 and 10.3 GHz. Special attention is paid to the layout issues for the high frequency design

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation