Baseband-processor for a passive UHF RFID transponder

This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID transponders, and proposes different techniques for reducing its power consumption. The processor has been implemented in a 0.35μm CMOS technology process using automatic tools for both the logic synthesis and layout. Post-layout simulations confirm the fully functionality of the prototype and predict a worst-case power consumption of only 2.9μA at 1.2V supply.Ministerio de Educación y Ciencia TEC2006-03022, TEC2009-08447Junta de Andalucía TIC-0281

Automatic Synthesis of VLSI Layout for CMOS Continuous-Time Filters

Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for signal drift. Parasitic directly influence signal integrity and the functionality of the circuit. The underlying problem, that the automatic VLSI layout programs face, is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods

Dynamic logic synthesis with application to self-timed pipelines.

This thesis describes a new method of designing multiple output dynamic logic suitable for an automatic synthesis procedure. A new cascode voltage switch logic synthesis method is derived with examples demonstrating the procedures. The procedures are summarized into 3 reduction rules. This method is modified to synthesize multiple output domino logic. A companion algorithm for handling Don\u27t care cases is also developed. Another algorithm for transforming a non-planar circuit into a planar circuit for use in automatic layout synthesis is presented. An alternate method of realizing cascode voltage switch logic is developed. It is a semi-custom cell design method. The cell uses almost one half the number of the transistors used in a full tree implementation. All of the new synthesis procedures are automated by a program written in PROGRAPH and C. A SRT self-timed divider is implemented to demonstrate the use of the new procedures. It is implemented in 3$\mu$m CMOS technology.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1993 .C455. Source: Masters Abstracts International, Volume: 32-02, page: 0679. Adviser: G. A. Jullien. Thesis (M.A.Sc.)--University of Windsor (Canada), 1993

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

A new partitioning approach for layout synthesis from register-transfer netlists

Most of the IC today are described and documented using heiarchical netlists. In addition to gates, latches, and flip-flops, these netlists include sliceable register-transfer components such as registers, counters, adders, ALUs, shifters, register files, and multiplexers. Usually, these components are decomposed into basic gates, latches, and flip-flops, and are laid out using standard cells. The standard cell architecture requires excessive routing area, and does not exploit the bit-sliced nature of register-transfer components. In this paper, we present a new sliced-layout architecture to alleviate the preceding problems. We also describe partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between blocks. This approach improves the overall area utilization and minimizes the total wire length

Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies

Layout area models for high-level synthesis

Traditionally, the common cost functions, the number of functional units, registers and selector inputs, are used in high level synthesis as quality measures. However, these traditional design quality measures may not reflect the real physical design. To establish quality measures based on the physical designs, we propose layout estimation models for two commonly used data path and control layout architectures. The results show that quality measures deriving from our models give an accurate prediction of the final layout. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

ToPoliNano: Nano-magnet Logic Circuits Design and Simulation

Among the emerging technologies Field-Coupled devices like Quantum dot Cellular Automata are particularly interesting. Of all the practical implementations of this principle NanoMagnet Logic shows many important features, such as a very low power consumption and the feasibility with up-to- date technology. However, its working principle, based on the interaction among neighbor cells, is quite different with respect to CMOS devices behavior. Dedicated design and simulation tools for this technology are necessary to further study this technology, but at the moment there are no such tools available in the scientific scenario. We present here ToPoliNano, a software developed as a design and simulation tool for NanoMagnet Logic, that can be easily adapted to many others emerging technologies, particularly to any kind of Field-Coupled devices. ToPoliNano allows to design circuits following a top-down approach similar to the one used in CMOS and to simulate them using a switch model specifically targeted for high complexity circuits. This tool greatly enhances the ability to analyze, explore and improve the design of Field- Coupled circuit