Subthreshold and gate leakage current analysis and reduction in VLSI circuits

CMOS technology has scaled aggressively over the past few decades in an effort to enhance functionality, speed and packing density per chip. As the feature sizes are scaling down to sub-100nm regime, leakage power is increasing significantly and is becoming the dominant component of the total power dissipation. Major contributors to the total leakage current in deep submicron regime are subthreshold and gate tunneling leakage currents. The leakage reduction techniques developed so far were mostly devoted to reducing subthreshold leakage. However, at sub-65nm feature sizes, gate leakage current grows faster and is expected to surpass subthreshold leakage current. In this work, an extensive analysis of the circuit level characteristics of subthreshold and gate leakage currents is performed at 45nm and 32nm feature sizes. The analysis provides several key observations on the interdependency of gate and subthreshold leakage currents. Based on these observations, a new leakage reduction technique is proposed that optimizes both the leakage currents. This technique identifies minimum leakage vectors for a given circuit based on the number of transistors in OFF state and their position in the stack. The effectiveness of the proposed technique is compared to most of the mainstream leakage reduction techniques by implementing them on ISCAS89 benchmark circuits. The proposed leakage reduction technique proved to be more effective in reducing gate leakage current than subthreshold leakage current. However, when combined with dual-threshold and variable-threshold CMOS techniques, substantial subthreshold leakage current reduction was also achieved. A total savings of 53% for subthreshold leakage current and 26% for gate leakage current are reported

Comparative Study of Leakage Reduction Techniques for Domino Logic Circuit

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Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

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Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits

In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits. In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement. We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique

LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Power management circuit: design and comparison of efficient techniques for ultra-low power analog switch and rectifier circuit

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores, Instrumentação e Microssistemas EletrónicosA presente dissertação de mestrado apresenta um estudo na área de CMOS em circuitos analógicos/digitais para extração e conversão de potência adequado para aplicações em energy harvesting. As principais contribuições científicas deste trabalho são: o desenvolvimento de circuitos de baixo consumo energético, tais como um interruptor analógico e um retificador que podem extrair e converter eficientemente a potência de saída do energy harvester. Com os dois circuitos apresentados na presente dissertação, é possível alimentar um nó de uma rede de sensores sem fios. Estes circuitos foram projetados utilizando a tecnologia CMOS de 130 nm e as respetivas simulações foram realizadas utilizando o software Cadence Virtuoso Analog Environment. Neste trabalho projetou-se novo interruptor analógico para aplicações em energy harvesting com especial atenção para a obtenção de um baixo consumo energético. A configuração apresentada consegue atingir uma baixa resistência, quando em condução (ON), e evitar correntes reversas indesejadas provenientes da carga. Os resultados das simulações revelam que o circuito: consome uma potência de 200.8 nW; atinge uma baixa resistência, quando em condução, de 216 Ω; gera uma baixa corrente de fuga de 44 pA. Assim sendo, é possível verificar que este circuito consegue operar com um baixo consumo, baixa tensão e com uma baixa frequência. Para além disso, o mesmo interruptor analógico consegue realizar a técnica de up-conversion dentro do circuito de controlo de potência, o que indica a possibilidade de o mesmo contribuir para uma aplicação real com energy harvesters vibracionais. O retificador em CMOS proposto é constituído por dois estágios: um passivo com um conversor de tensão negativa; e um outro estágio com um díodo ativo controlado por um circuito de cancelamento de threshold. O primeiro estágio é responsável por retificar completamente o sinal de entrada com uma queda de tensão de 1 mV, enquanto que o último tem a função de reduzir a corrente reversa indesejada, o que consequentemente consegue aumentar a potência transferida para a carga. Deste modo, o circuito consegue atingir uma eficiência em tensão e potência de 99 % e 90%, respetivamente, para um sinal de entrada com 0.45 V de amplitude e para cargas resistivas de valor baixo. Ainda assim, este circuito consegue funcionar a uma banda de frequências desde os 800 Hz até 51.2 kHz, o que se revela ser promissor para a aplicação prática deste projeto.The master dissertation presents a study in the area of mixed analog/digital CMOS power extraction and conversion circuits for Power Management Circuit (PMC) suitable for energy harvesting applications. The main contributions of the work are the development of low power circuits, such as an Analog Switch and a Rectifier, that can efficiently extract and convert the output power of the vibrational energy harvester into suitable electric energy for powering a Wireless Sensor Network (WSN) node. The circuit components were fully designed in the standard 130 nm CMOS process, and the respective simulation experiments were carried out using the Cadence Virtuoso Analog Environment. A new Analog Switch was designed for energy harvesting applications with special consideration for achieving low power consumption. The proposed structure can achieve a reduced ON-resistance and avoid the reverse leakage current from the load. Simulation results reveal a power consumption of about 200.8 nW, a low ON-resistance of 244.6 Ω, and a low leakage current of around 44 pA, which indicates that the analog switch has features of low power consumption, low voltage, and low-frequency operation. Furthermore, this switching circuit is suitable for performing the up-conversion technique in the PMC, which may contribute to the real application of vibrational energy harvesters. The proposed CMOS Rectifier consists of two stages, one passive stage with a negative voltage converter, and another stage with an active diode controlled by a threshold cancellation circuit. The former stage conducts the signal full-wave rectification with a voltage drop of 1 mV while the latter reduces the reverse leakage current, consequently enhancing the output power delivered to the ohmic load. As a result, the rectifier can achieve a voltage and a power conversion efficiency of over 99 % and 90 %, respectively, for an input voltage of 0.45 V and low ohmic loads. This circuit works for an operating frequency range from 800 Hz to 51.2 kHz, which is promising for practical applications