Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems

The complexity of computation hardware has increased at an unprecedented rate for the last few decades. On the computer chip level, we have entered the era of multi/many-core processors made of billions of transistors. With transistor budget of this scale, many functions are integrated into a single chip. As such, chips today consist of many heterogeneous cores with intensive interaction among these cores. On the circuit level, with the end of Dennard scaling, continuously shrinking process technology has imposed a grand challenge on power density. The variation of circuit further exacerbated the problem by consuming a substantial time margin. On the system level, the rise of Warehouse Scale Computers and Data Centers have put resource management into new perspective. The ability of dynamically provision computation resource in these gigantic systems is crucial to their performance. In this thesis, three different resource management algorithms are discussed. The first algorithm assigns adaptivity resource to circuit blocks with a constraint on the overhead. The adaptivity improves resilience of the circuit to variation in a cost-effective way. The second algorithm manages the link bandwidth resource in application specific Networks-on-Chip. Quality-of-Service is guaranteed for time-critical traffic in the algorithm with an emphasis on power. The third algorithm manages the computation resource of the data center with precaution on the ill states of the system. Q-learning is employed to meet the dynamic nature of the system and Linear Temporal Logic is leveraged as a tool to describe temporal constraints. All three algorithms are evaluated by various experiments. The experimental results are compared to several previous work and show the advantage of our methods

Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems

The complexity of computation hardware has increased at an unprecedented rate for the last few decades. On the computer chip level, we have entered the era of multi/many-core processors made of billions of transistors. With transistor budget of this scale, many functions are integrated into a single chip. As such, chips today consist of many heterogeneous cores with intensive interaction among these cores. On the circuit level, with the end of Dennard scaling, continuously shrinking process technology has imposed a grand challenge on power density. The variation of circuit further exacerbated the problem by consuming a substantial time margin. On the system level, the rise of Warehouse Scale Computers and Data Centers have put resource management into new perspective. The ability of dynamically provision computation resource in these gigantic systems is crucial to their performance. In this thesis, three different resource management algorithms are discussed. The first algorithm assigns adaptivity resource to circuit blocks with a constraint on the overhead. The adaptivity improves resilience of the circuit to variation in a cost-effective way. The second algorithm manages the link bandwidth resource in application specific Networks-on-Chip. Quality-of-Service is guaranteed for time-critical traffic in the algorithm with an emphasis on power. The third algorithm manages the computation resource of the data center with precaution on the ill states of the system. Q-learning is employed to meet the dynamic nature of the system and Linear Temporal Logic is leveraged as a tool to describe temporal constraints. All three algorithms are evaluated by various experiments. The experimental results are compared to several previous work and show the advantage of our methods

Timing Closure in Chip Design

Achieving timing closure is a major challenge to the physical design of a computer chip. Its task is to find a physical realization fulfilling the speed specifications. In this thesis, we propose new algorithms for the key tasks of performance optimization, namely repeater tree construction; circuit sizing; clock skew scheduling; threshold voltage optimization and plane assignment. Furthermore, a new program flow for timing closure is developed that integrates these algorithms with placement and clocktree construction. For repeater tree construction a new algorithm for computing topologies, which are later filled with repeaters, is presented. To this end, we propose a new delay model for topologies that not only accounts for the path lengths, as existing approaches do, but also for the number of bifurcations on a path, which introduce extra capacitance and thereby delay. In the extreme cases of pure power optimization and pure delay optimization the optimum topologies regarding our delay model are minimum Steiner trees and alphabetic code trees with the shortest possible path lengths. We presented a new, extremely fast algorithm that scales seamlessly between the two opposite objectives. For special cases, we prove the optimality of our algorithm. The efficiency and effectiveness in practice is demonstrated by comprehensive experimental results. The task of circuit sizing is to assign millions of small elementary logic circuits to elements from a discrete set of logically equivalent, predefined physical layouts such that power consumption is minimized and all signal paths are sufficiently fast. In this thesis we develop a fast heuristic approach for global circuit sizing, followed by a local search into a local optimum. Our algorithms use, in contrast to existing approaches, the available discrete layout choices and accurate delay models with slew propagation. The global approach iteratively assigns slew targets to all source pins of the chip and chooses a discrete layout of minimum size preserving the slew targets. In comprehensive experiments on real instances, we demonstrate that the worst path delay is within 7% of its lower bound on average after a few iterations. The subsequent local search reduces this gap to 2% on average. Combining global and local sizing we are able to size more than 5.7 million circuits within 3 hours. For the clock skew scheduling problem we develop the first algorithm with a strongly polynomial running time for the cycle time minimization in the presence of different cycle times and multi-cycle paths. In practice, an iterative local search method is much more efficient. We prove that this iterative method maximizes the worst slack, even when restricting the feasible schedule to certain time intervals. Furthermore, we enhance the iterative local approach to determine a lexicographically optimum slack distribution. The clock skew scheduling problem is then generalized to allow for simultaneous data path optimization. In fact, this is a time-cost tradeoff problem. We developed the first combinatorial algorithm for computing time-cost tradeoff curves in graphs that may contain cycles. Starting from the lowest-cost solution, the algorithm iteratively computes a descent direction by a minimum cost flow computation. The maximum feasible step length is then determined by a minimum ratio cycle computation. This approach can be used in chip design for several optimization tasks, e.g. threshold voltage optimization or plane assignment. Finally, the optimization routines are combined into a timing closure flow. Here, the global placement is alternated with global performance optimization. Netweights are used to penalize the length of critical nets during placement. After the global phase, the performance is improved further by applying more comprehensive optimization routines on the most critical paths. In the end, the clock schedule is optimized and clocktrees are inserted. Computational results of the design flow are obtained on real-world computer chips

Algorithms for Circuit Sizing in VLSI Design

One of the key problems in the physical design of computer chips, also known as integrated circuits, consists of choosing a  physical layout  for the logic gates and memory circuits (registers) on the chip. The layouts have a high influence on the power consumption and area of the chip and the delay of signal paths.  A discrete set of predefined layouts  for each logic function and register type with different physical properties is given by a library. One of the most influential characteristics of a circuit defined by the layout is its size. In this thesis we present new algorithms for the problem of choosing sizes for the circuits and its continuous relaxation,  and  evaluate these in theory and practice. A popular approach is based on Lagrangian relaxation and projected subgradient methods. We show that seemingly heuristic modifications that have been proposed for this approach can be theoretically justified by applying the well-known multiplicative weights algorithm. Subsequently, we propose a new model for the sizing problem as a min-max resource sharing problem. In our context, power consumption and signal delays are represented by resources that are distributed to customers. Under certain assumptions we obtain a polynomial time approximation for the continuous relaxation of the sizing problem that improves over the Lagrangian relaxation based approach. The new resource sharing algorithm has been implemented as part of the BonnTools software package which is developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. Our experiments on the ISPD 2013 benchmarks and state-of-the-art microprocessor designs provided by IBM illustrate that the new algorithm exhibits more stable convergence behavior compared to a Lagrangian relaxation based algorithm. Additionally, better timing and reduced power consumption was achieved on almost all instances. A subproblem of the new algorithm consists of finding sizes minimizing a weighted sum of power consumption and signal delays. We describe a method that approximates the continuous relaxation of this problem in polynomial time under certain assumptions. For the discrete problem we provide a fully polynomial approximation scheme under certain assumptions on the topology of the chip. Finally, we present a new algorithm for timing-driven optimization of registers. Their sizes and locations on a chip are usually determined during the clock network design phase, and remain mostly unchanged afterwards although the timing criticalities on which they were based can change. Our algorithm permutes register positions and sizes within so-called  clusters  without impairing the clock network such that it can be applied late in a design flow. Under mild assumptions, our algorithm finds an optimal solution which maximizes the worst cluster slack. It is implemented as part of the BonnTools and improves timing of registers on state-of-the-art microprocessor designs by up to 7.8% of design cycle time. </div

Non-convex resource allocation in communication networks

The continuously growing number of applications competing for resources in current communication networks highlights the necessity for efficient resource allocation mechanisms to maximize user satisfaction. Optimization Theory can provide the necessary tools to develop such mechanisms that will allocate network resources optimally and fairly among users. However, the resource allocation problem in current networks has characteristics that turn the respective optimization problem into a non-convex one. First, current networks very often consist of a number of wireless links, whose capacity is not constant but follows Shannon capacity formula, which is a non-convex function. Second, the majority of the traffic in current networks is generated by multimedia applications, which are non-concave functions of rate. Third, current resource allocation methods follow the (bandwidth) proportional fairness policy, which when applied to networks shared by both concave and non-concave utilities leads to unfair resource allocations. These characteristics make current convex optimization frameworks inefficient in several aspects. This work aims to develop a non-convex optimization framework that will be able to allocate resources efficiently for non-convex resource allocation formulations. Towards this goal, a necessary and sufficient condition for the convergence of any primal-dual optimization algorithm to the optimal solution is proven. The wide applicability of this condition makes this a fundamental contribution for Optimization Theory in general. A number of optimization formulations are proposed, cases where this condition is not met are analysed and efficient alternative heuristics are provided to handle these cases. Furthermore, a novel multi-sigmoidal utility shape is proposed to model user satisfaction for multi-tiered multimedia applications more accurately. The advantages of such non-convex utilities and their effect in the optimization process are thoroughly examined. Alternative allocation policies are also investigated with respect to their ability to allocate resources fairly and deal with the non-convexity of the resource allocation problem. Specifically, the advantages of using Utility Proportional Fairness as an allocation policy are examined with respect to the development of distributed algorithms, their convergence to the optimal solution and their ability to adapt to the Quality of Service requirements of each application

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

Combinatorial optimization is a complex engineering subject. Although formulation often depends on the nature of problems that differs from their setup, design, constraints, and implications, establishing a unifying framework is essential. This dissertation investigates the unique features of three important optimization problems that can span from small-scale design automation to large-scale power system planning: (1) Feeder remote terminal unit (FRTU) planning strategy by considering the cybersecurity of secondary distribution network in electrical distribution grid, (2) physical-level synthesis for microfluidic lab-on-a-chip, and (3) discrete gate sizing in very-large-scale integration (VLSI) circuit. First, an optimization technique by cross entropy is proposed to handle FRTU deployment in primary network considering cybersecurity of secondary distribution network. While it is constrained by monetary budget on the number of deployed FRTUs, the proposed algorithm identi?es pivotal locations of a distribution feeder to install the FRTUs in different time horizons. Then, multi-scale optimization techniques are proposed for digital micro?uidic lab-on-a-chip physical level synthesis. The proposed techniques handle the variation-aware lab-on-a-chip placement and routing co-design while satisfying all constraints, and considering contamination and defect. Last, the first fully polynomial time approximation scheme (FPTAS) is proposed for the delay driven discrete gate sizing problem, which explores the theoretical view since the existing works are heuristics with no performance guarantee. The intellectual contribution of the proposed methods establishes a novel paradigm bridging the gaps between professional communities

Development of transportation and supply chain problems with the combination of agent-based simulation and network optimization

Demand drives a different range of supply chain and logistics location decisions, and agent-based modeling (ABM) introduces innovative solutions to address supply chain and logistics problems. This dissertation focuses on an agent-based and network optimization approach to resolve those problems and features three research projects that cover prevalent supply chain management and logistics problems. The first case study evaluates demographic densities in Norway, Finland, and Sweden, and covers how distribution center (DC) locations can be established using a minimizing trip distance approach. Furthermore, traveling time maps are developed for each scenario. In addition, the Nordic area consisting of those three countries is analyzed and five DC location optimization results are presented. The second case study introduces transportation cost modelling in the process of collecting tree logs from several districts and transporting them to the nearest collection point. This research project presents agent-based modelling (ABM) that incorporates comprehensively the key elements of the pick-up and delivery supply chain model and designs the components as autonomous agents communicating with each other. The modelling merges various components such as GIS routing, potential facility locations, random tree log pickup locations, fleet sizing, trip distance, and truck and train transportation. The entire pick-up and delivery operation are modeled by ABM and modeling outcomes are provided by time series charts such as the number of trucks in use, facilities inventory and travel distance. In addition, various scenarios of simulation based on potential facility locations and truck numbers are evaluated and the optimal facility location and fleet size are identified. In the third case study, an agent-based modeling strategy is used to address the problem of vehicle scheduling and fleet optimization. The solution method is employed to data from a real-world organization, and a set of key performance indicators are created to assess the resolution's effectiveness. The ABM method, contrary to other modeling approaches, is a fully customized method that can incorporate extensively various processes and elements. ABM applying the autonomous agent concept can integrate various components that exist in the complex supply chain and create a similar system to assess the supply chain efficiency.Tuotteiden kysyntä ohjaa erilaisia toimitusketju- ja logistiikkasijaintipäätöksiä, ja agenttipohjainen mallinnusmenetelmä (ABM) tuo innovatiivisia ratkaisuja toimitusketjun ja logistiikan ongelmien ratkaisemiseen. Tämä väitöskirja keskittyy agenttipohjaiseen mallinnusmenetelmään ja verkon optimointiin tällaisten ongelmien ratkaisemiseksi, ja sisältää kolme tapaustutkimusta, jotka voidaan luokitella kuuluvan yleisiin toimitusketjun hallinta- ja logistiikkaongelmiin. Ensimmäinen tapaustutkimus esittelee kuinka käyttämällä väestötiheyksiä Norjassa, Suomessa ja Ruotsissa voidaan määrittää strategioita jakelukeskusten (DC) sijaintiin käyttämällä matkan etäisyyden minimoimista. Kullekin skenaariolle kehitetään matka-aikakartat. Lisäksi analysoidaan näistä kolmesta maasta koostuvaa pohjoismaista aluetta ja esitetään viisi mahdollista sijaintia optimointituloksena. Toinen tapaustutkimus esittelee kuljetuskustannusmallintamisen prosessissa, jossa puutavaraa kerätään useilta alueilta ja kuljetetaan lähimpään keräyspisteeseen. Tämä tutkimusprojekti esittelee agenttipohjaista mallinnusta (ABM), joka yhdistää kattavasti noudon ja toimituksen toimitusketjumallin keskeiset elementit ja suunnittelee komponentit keskenään kommunikoiviksi autonomisiksi agenteiksi. Mallinnuksessa yhdistetään erilaisia komponentteja, kuten GIS-reititys, mahdolliset tilojen sijainnit, satunnaiset puunhakupaikat, kaluston mitoitus, matkan pituus sekä monimuotokuljetukset. ABM:n avulla mallinnetaan noutojen ja toimituksien koko ketju ja tuloksena saadaan aikasarjoja kuvaamaan käytössä olevat kuorma-autot, sekä varastomäärät ja ajetut matkat. Lisäksi arvioidaan erilaisia simuloinnin skenaarioita mahdollisten laitosten sijainnista ja kuorma-autojen lukumäärästä sekä tunnistetaan optimaalinen toimipisteen sijainti ja tarvittava autojen määrä. Kolmannessa tapaustutkimuksessa agenttipohjaista mallinnusstrategiaa käytetään ratkaisemaan ajoneuvojen aikataulujen ja kaluston optimoinnin ongelma. Ratkaisumenetelmää käytetään dataan, joka on peräisin todellisesta organisaatiosta, ja ratkaisun tehokkuuden arvioimiseksi luodaan lukuisia keskeisiä suorituskykyindikaattoreita. ABM-menetelmä, toisin kuin monet muut mallintamismenetelmät, on täysin räätälöitävissä oleva menetelmä, joka voi sisältää laajasti erilaisia prosesseja ja elementtejä. Autonomisia agentteja soveltava ABM voi integroida erilaisia komponentteja, jotka ovat olemassa monimutkaisessa toimitusketjussa ja luoda vastaavan järjestelmän toimitusketjun tehokkuuden arvioimiseksi yksityiskohtaisesti.fi=vertaisarvioitu|en=peerReviewed

FracBot: Design of wireless underground sensor networks for mapping hydraulic fractures and determining reservoir parameters in unconventional systems

Wireless underground sensor networks (WUSNs) enable a wide variety of emerging applications that are not possible with current underground monitoring techniques, which require miniaturized wireless sensor systems for mapping hydraulic fractures, monitoring unconventional reservoirs and measuring other wellbore parameters. We call these devices FracBots (Fracture Robots), an extension of RFID (Radio Frequency IDentifcation) tags that realize WUSNs for mapping and characterization of hydraulic fractures in unconventional reservoirs. The objective of this thesis is to design fully integrated magnetic induction (MI)-based FracBots (WUSNs) that enable reliable and e fficient wireless communications in underground oil reservoirs for performing the in-situ monitoring of oil reservoirs. This is very crucial for determining the sweet spot of oil and natural gas reserves. To this end, we have contributed in four areas as follows: fi rst, we develop a novel cross-layer communication framework for MI-based FracBot networks in dynamically changing underground environments. The framework combines a joint selection of modulation, channel coding, power control and a geographic forwarding paradigm. Second, we develop a novel MI-based localization framework that exploits the unique properties of MI- eld to determine the locations of the randomly deployed FracBot nodes in oil reservoirs. Third, we develop an accurate energy framework of a linear FracBot network topology that generates feasible nodes' transmission rates and network topology while always guaranteeing su fficient energy. Then, we design, develop, and fabricate MI-based FracBot nodes. Finally, to validate the performance of our solutions in our produced prototype of FracBot nodes, we develop a physical MI-based WUSN testbed.Ph.D

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi