Flexible glass substrates with via holes for TFT backplanes

This paper looks at flexible glass substrates with via holes for TFT backplane

Architectural level delay and leakage power modelling of manufacturing process variation

PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the estimation of circuit delay and power dissipation, and will gain more importance in the future as device scaling continues in order to satisfy market place demands for circuits with greater performance and functionality per unit area. Statistical modelling and analysis approaches have been widely used to reflect the effects of a variety of variational process parameters on system performance factor which will be described as probability density functions (PDFs). At present most of the investigations into statistical models has been limited to small circuits such as a logic gate. However, the massive size of present day electronic systems precludes the use of design techniques which consider a system to comprise these basic gates, as this level of design is very inefficient and error prone. This thesis proposes a methodology to bring the effects of process variation from transistor level up to architectural level in terms of circuit delay and leakage power dissipation. Using a first order canonical model and statistical analysis approach, a statistical cell library has been built which comprises not only the basic gate cell models, but also more complex functional blocks such as registers, FIFOs, counters, ALUs etc. Furthermore, other sensitive factors to the overall system performance, such as input signal slope, output load capacitance, different signal switching cases and transition types are also taken into account for each cell in the library, which makes it adaptive to an incremental circuit design. The proposed methodology enables an efficient analysis of process variation effects on system performance with significantly reduced computation time compared to the Monte Carlo simulation approach. As a demonstration vehicle for this technique, the delay and leakage power distributions of a 2-stage asynchronous micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method can predict the delay and leakage power distribution with less than 5% error and at least 50,000 times faster computation time compare to 5000-sample SPICE based Monte Carlo simulation. The methodology presented here for modelling process variability plays a significant role in Design for Manufacturability (DFM) by quantifying the direct impact of process variations on system performance. The advantages of being able to undertake this analysis at a high level of abstraction and thus early in the design cycle are two fold. First, if the predicted effects of process variation render the circuit performance to be outwith specification, design modifications can be readily incorporated to rectify the situation. Second, knowing what the acceptable limits of process variation are to maintain design performance within its specification, informed choices can be made regarding the implementation technology and manufacturer selected to fabricate the design

Chemical Current-Conveyor: a new approach in biochemical computation

Biochemical sensors that are low cost, small in size and compatible with integrated circuit technology play an essential part in the drive towards personalised healthcare and the research described in this thesis is concerned with this area of medical instrumentation. A new biochemical measurement system able to sense key properties of biochemical fluids is presented. This new integrated circuit biochemical sensor, called the Chemical Current-Conveyor, uses the ion sensitive field effect transistor as the input sensor combined with the current-conveyor, an analog building-block, to produce a range of measurement systems. The concept of the Chemical Current-Conveyor is presented together with the design and subsequent fabrication of a demonstrator integrated circuit built on conventional 0.35μm CMOS silicon technology. The silicon area of the Chemical Current-Conveyor is (92μm x 172μm) for the N-channel version and (99μm x 165μm) for the P-channel version. Power consumption for the N-channel version is 30μW and 43μW for the P-channel version with a full load of 1MΩ. The maximum sensitivity achieved for pH measurement was 46mV per pH. The potential of the Chemical Current Conveyor as a versatile biochemical integrated circuit, able to produce output information in an appropriate form for direct clinical use has been confirmed by applications including measurement of (i) pH, (ii) buffer index ( ), (iii) urea, (iv) creatinine and (v) urea:creatinine ratio. In all five cases the device has been demonstrated successfully, confirming the validity of the original aim of this research project, namely to produce a versatile and flexible analog circuit for many biochemical measurement applications. Finally, the thesis closes with discussion of another potential application area for the Chemical Current Conveyor and the main contributions can be summarised by the design and development of the first: ISFET based current-conveyor biochemical sensor, called 'Chemical Current Conveyor, CCCII+' has been designed and developed. It is a general purpose biochemical analog building-block for several biochemical measurements. Real-time buffer capacity measurement system, based on the CCCII+, which exploits the imbedded analog computation capability of the CCCII+. Real-time enzyme based CCCII+ namely, Creatinine-CCCII+ and Urea-CCCII+ for real-time monitoring system of renal system. The system can provide outputs of 3 important parameters of the renal system, namely (i) urea concentration, (ii) creatinine concentration, and (ii) urea to creatinine ratio

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

4MW Class High Power Density Generator for Future Hybrid-Electric Aircraft

This paper describes the underpinning research, development, construction and testing of a 4MW multi-three phase generator designed for a hybrid-electric aircraft propulsion system demonstrator. The aim of the work is to demonstrate gravimetric power densities around 20 kW/kg, as required for multi-MW aircraft propulsion systems. The key design choices, development procedures and trade-offs, together with the experimental testing of this electrical machine connected to an active rectifier are presented. A time-efficient analytical approach to the down-selection of various machine configurations, geometrical variables, different active and passive materials and different thermal management options is first presented. A detailed design approach based on 3D Finite Element Analysis (FEA) is then presented for the final design. Reduced power tests are carried out on a full scale 4 MW machine prototype, validating the proposed design. The experimental results are in good agreement with simulation and show significant progress in the field of high power density electrical machines at the targeted power rating

Conception, réalisation et modélisation de microcapteurs pour l'analyse biochimique. Application à la détection de l'urée

Les récents développements dans l'analyse chimique et biochimique, grâce à la technologie des ChemFETs, ont permis de proposer un large champ d'application. Ces composants ont besoin néanmoins d'être développés pour des applications médicales et agroalimentaires comme la transduction, l'intégration de couches sensibles et l'intégration de l'électrode de référence. Au cours de cette thèse, une étude sur l'intégration d'une microélectrode de référence a été réalisée pour permettre de concevoir une puce ChemFET tout intégrée, avec les techniques de la microélectronique. Cette microélectrode doit imposer un potentiel stable au milieu d'analyse, ayant une faible dérive temporelle, et une longue durée de vie. Ainsi, nos travaux ont conduit au développement d'un nouveau procédé de fabrication de puce pH-ChemFET. Ces nouvelles structures ont été réalisées au sein de la centrale du LAAS- CNRS et validées par leurs caractérisations. La compréhension des phénomènes interagissants, la prévision du fonctionnement, l'influence de l'environnement passent par la modélisation et la simulation. Les modèles existant des pH-ChemFET sont nombreux et robustes. Cependant, concernant les détecteurs enzymatiques EnFETs, il n'existe pas de modèle intégrant tous les phénomènes physico-chimiques. Ainsi, nous avons développé un modèle intégrant la diffusion, la cinétique enzymatique, les équations acido-basiques, le flux, la réponse potentiometrique. Ce modèle a permis la compréhension des mécanismes physiques et d'étudier l'impact des différentes grandeurs influentes. A partir de ce modèle adaptable aux différents capteurs enzymatiques, des EnFETs ont été ainsi réalisées. Les caractérisations de ces détecteurs ont permis par la concordance des résultats expérimentaux et des résultats de simulation, de montrer la validité et la robustesse du modèle.Recent developments in chemical and biochemical analysis have allowed its use to a wide variety of applications, thanks to the ChemFET technology. However, several aspects of these components still need to be developed for use in medical and food-industry applications, like selectivity and sensitivity, as well as technological integration of the sensitive layers and a reference electrode. In this thesis, a study on the integration of a reference microelectrode was conducted to allow for the design of a fully integrated ChemFET chip fabricated with standard microelectronics processes. The microelectrode must apply a constant potential in the media to be analyzed, with low temporal drift, and long life. Thus, our work has led to the development of a new chip manufacturing process for pH-ChemFETs. These new structures have been fabricated in LAAS-CNRS and their function validated by their characterizations. More insight on the interacting phenomena and the influence of environmental parameters can be gained by modeling and simulation. Existing models of pH-CHEMFETS are numerous and robust. However, for enzymatic EnFETs detectors, there is no model that integrates all the physico-chemical interactions. Thus, we have developed a model that incorporates diffusion, enzyme kinetics, acid-base equations, flow and potentiometric response. The model has allowed the understanding of physical mechanisms and to study the impact of each input parameter. This model which can be adaptad to suit different types of enzymatic sensors has been applied to the fabricated EnFETs. The good agreement between experimental results and simulation demonstrate the validity and robustness of the proposed model

DYNAMIC MAGNETIC EFFECTS IN AMORPHOUS MICROWIRES FOR SENSORS AND CODING APPLICATIONS

This work is devoted to the study of the dynamic properties of magnetic amorphous wires, in particular, glass-coated microwires, which have small diameters (5-30 microns), outstanding soft magnetic behaviour with a high permeability and low coercivity, yet, possess a well-defined magnetic structure. First part of my PhD research has been devoted to the investigation of a bi-stable magnetisation reversal in glass-coated amorphous microwires. In contrast to traditional approaches, where characteristics of the magnetisation reversal are analysed as a consequence of the eddy current effect, l have applied stochastic methods for modelling the remagnetisation reversal in the microwires with axial anisotropy. While the eddy current approach, widely discussed in literature, was based on the single domain model, proposed stochastic approach takes into account a multi-domain state of studied samples. A modified stochastic Neel-Brown model of the magnetisation reversal has been proposed enabling the explanation of number of characteristic parameters of the microwires with axial magnetisation. Such important parameters of Barkhausen discontinuity as a mean switching field and a standard deviation of the switching field distribution have been investigated experimentally for understanding the influence of extrinsic factors such as a slew rate of the alternating magnetic field on applications operation. A deep understanding of the remagnetisation process in amorphous the microwires with axial anisotropy was successfully applied in development of a new type of the remote magnetic interrogation system. My reading system allows the large Barkhausen jump to be detected without actual contact between the magnetic microwire and the magnetic field detector. Experiments show that the detection will be possible at a distance of approximately 100-150 mm from the detecting sensor. A very low cost and easily repetitive amorphous microwires with axial anisotropy are . incontrovertibly best materials for Electronic Article Surveillance (EAS) applications. During the study of the microwires with axial anisotropy and development of the application based on them, I took part in the investigation of unusual coding methods of the amorphous microwires using a localised laser annealing treatment. This treatment produces a multi-pulse code within the wire and therefore adds to the information contained within the wire, improving reliability and security. I developed and used a magnetic interrogation system allowing an accurate and reliable test and analysis of the studied samples. The second part of my PhD research has included investigations of microwires with circumferential and helical anisotropies. The main interest in these materials is due to their applications for high-performance magnetic and stress sensors. Within this research project, the microwires with circumferential/helical anisotropy have been studied in a broad range of frequencies. A number of dynamic effects have been experimentally obtained and analysed. In particular, a detailed investigation of dynamic circular hysteresis (10kHz-300kHz) has been carried out allowing explanation of different behaviour of the materials with circumferential/helical anisotropy at different frequencies. The experimental curves are proposed to be analysed in terms of field dependence of characteristic permeabilities: domain wall displacements (reversible and irreversible) and magnetisation rotation. It was established that these permeabilities have different field behaviour. That explains different MI patterns at relatively low frequencies (less than a few MHz) and relatively high frequencies (more than 10 MHz). Further, some special features of the Magneto-Impedance effect in the microwires with a circumferential anisotropy such as off-diagonal impedance and microwave impedance have been considered. In this research, the former presents a considerable interest for development of linear magnetic sensors and the latter can find application in tuneable microwave materials and devices. As a result of this study several types of linear, bi-directional MI sensors were developed. I also developed new MI sensing approaches (such as off-diagonal response) and a new high performance detection technique allowing us to improve sensitivity, bandwidth, and linearity at low cost and simple construction .. The last part of the PhD research has been devoted to an investigation of the stress-impedance in the ultra high-frequency (UHF) band (300MHz-3 GHz). Based on the experimental investigation, a new type of a stress-sensitive composite material is proposed. The microwave effective permittivity of such material depends on mechanical stresses. These composite materials opens up new possibilities for remote monitoring of stress with the use of microwave "free-space" techniques. This kind of composite material can be characterised as a "sensing medium", which images the mechanical stress distribution inside construction or on its surface

Sincronização em sistemas integrados a alta velocidade

Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm

Emerging Technologies - NanoMagnets Logic (NML)

In the last decades CMOS technology has ruled the electronic scenario thanks to the constant scaling of transistor sizes. With the reduction of transistor sizes circuit area decreases, clock frequency increases and power consumption decreases accordingly. However CMOS scaling is now approaching its physical limits and many believe that CMOS technology will not be able to reach the end of the Roadmap. This is mainly due to increasing difficulties in the fabrication process, that is becoming very expensive, and to the unavoidable impact of leakage losses, particularly thanks to gate tunnel current. In this scenario many alternative technologies are studied to overcome the limitations of CMOS transistors. Among these possibilities, magnetic based technologies, like NanoMagnet Logic (NML) are among the most interesting. The reason of this interest lies in their magnetic nature, that opens up entire new possibilities in the design of logic circuits, like the possibility to mix logic and memory in the same device. Moreover they have no standby power consumption and potentially a much lower power consumption of CMOS transistors. In literature NML logic is well studied and theoretical and experimental proofs of concept were already found. However two important points are not enough considered in the analysis approach followed by most of the work in literature. First of all, no complex circuits are analyzed. NML logic is very different from CMOS technologies, so to completely understand the potential of this technology it is mandatory to investigate complex architectures. Secondly, most of the solutions proposed do not take into account the constraints derived from fabrication process, making them unrealistic and difficult to be fabricated experimentally. This thesis focuses therefore on NML logic keeping into account these two important limitations in the research approach followed in literature. The aim is to obtain a complete and accurate overview of NML logic, finding realistic circuital solutions and trying to improve at the same time their performance. After a brief and complete introduction (Chapter 1), the thesis is divided in two parts, which cover the two fundamental points followed in this three years of research: A circuits architecture analysis and a technological analysis. In the architecture analysis first an innovative VHDL model is described in Chapter 2. This model is extensively used in the analysis because it allows fast simulation of complex circuits, with, at the same time, the possibility to estimate circuit per- formance, like area and power consumption. In Chapter 3 the problem of signals synchronization in complex NML circuits is analyzed and solved, using as benchmark a simple but complete NML microprocessor. Different solutions based on asynchronous logic are studied and a new asynchronous solution, specifically designed to exploit the potential of NML logic, is developed. In Chapter 4 the layout of NML circuits is studied on a more physical level, considering the limitations of fabrication processes. The layout of NML circuits is therefore changed accordingly to these constraints. Secondly CMOS circuits architectures are compared to more simple architectures, evaluating therefore which one is more suited for NML logic. Finally the problem of interconnections in NML technology is analyzed and solutions to improve it are found. In Chapter 5 the problem of feedback signals in heavy pipelined technologies, like NML, is studied. Solutions to improve performances and synchronize signals are developed. Systolic arrays are then analyzed as possible candidate to exploit NML potential. Finally in Chapter 6 ToPoliNano, a simulator dedicated to NML and other emerging technologies, that we are developing, is described. This simulator allows to follow the same top-down approach followed for CMOS technology. The layout generator and the simulation engine are detailed described. In the first chapter of the technological analysis (Chapter 7), the performance of NML logic is explored throughout low level simulations. The aim is to understand if these circuits can be fabricated with optical lithography, allowing therefore the commercial development of NML logic. Basic logic gates and the clock system are there analyzed from a low level perspective. In Chapter 8 an innovative electric clock system for NML technology is shown and the first experimental results are reported. This clock system allows to achieve true low power for NML technology, obtaining a reduction of power consumption of 20 times considering the best CMOS transistors available. This power consumption takes into account all the losses, also the clock system losses. Moreover the solution presented can be fabricated with current technological processes. The research work behind this thesis represents an important breakthrough in NML logic. The solutions here presented allow the design and fabrication of complex NML circuits, considering the particular characteristics of this technology and considerably improving the performance. Moreover the technological solutions here presented allow the design and fabrication of circuits with available fabrication process with a considerable advantage over CMOS in terms of power consumption. This thesis represents therefore a considerable step froward in the study and development of NML technolog

Intelligent and Efficient Transport Systems

The aim of this book is to present a number of digital and technology solutions to real-world problems across transportation sectors and infrastructures. Nine chapters have been well prepared and organized with the core topics as follows: -A guideline to evaluate the energy efficiency of a vehicle -A guideline to design and evaluate an electric propulsion system -Potential opportunities for intelligent transportation systems and smart cities -The importance of system control and energy-power management in transportation systems and infrastructures -Bespoke modeling tools and real-time simulation platforms for transportation system development This book will be useful to a wide range of audiences: university staff and students, engineers, and business people working in relevant fields