Design, Characterization And Analysis Of Electrostatic Discharge (esd) Protection Solutions In Emerging And Modern Technologies

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the en

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Neurostimulateur hautement intégré et nouvelle stratégie de stimulation pour améliorer la miction chez les paraplégiques

RÉSUMÉ Une lésion de la moelle épinière est un problème dévastateur médicalement et socialement. Pour la population des États-Unis seulement, il y a près de 10 000 nouveaux cas chaque année. A cause des nombreux types de lésions possibles, divers degrés de dysfonctionnement du bas appareil urinaire peuvent en découler. Une lésion est dite complète lors d’une perte totale des fonctions sensorielles et motrices volontaires en dessous du niveau de la lésion. Une lésion incomplète implique que certaines activités sensorielles et/ou motrices soient encore présentes. Si la lésion se produit au dessus du cône médullaire, la vessie développera une hyperréflexie qui se manifeste par des contractions réflexes non-inhibées. Ces contractions peuvent être accompagnées d’une augmentation de l’activité du sphincter externe. Par conséquent, cela mène à un état d’obstruction fonctionnelle de la vessie, qui induit une forte pression intravésicale à chacune des contractions réflexes et qui peut potentiellement endommager le haut appareil urinaire. Dans ce contexte, la neurostimulation est l'une des techniques les plus prometteuses pour la réhabilitation de la vessie chez les patients ayant subi une lésion de la moelle épinière. Le seul neurostimulateur implantable commercialisé, ciblant l'amélioration de la miction et ayant obtenu des résultats satisfaisants, nécessite une rhizotomie (section de certains nerfs) afin de réduire la dyssynergie entre la vessie et le sphincter. Cependant, la rhizotomie est irréversible et peut abolir les réflexes sexuels, de défécation ainsi que les sensations sacrales si encore présents dans le cas de lésions incomplètes. Afin d'éviter la rhizotomie, nous proposons une nouvelle stratégie de stimulation multi-site appliquée aux racines sacrées, et basée sur le blocage de la conduction des nerfs à l'aide d'une stimulation à haute fréquence comme alternative à la rhizotomie. Cette approche permettrait une meilleure miction en augmentant sélectivement la contraction de la vessie et en diminuant la dyssynergie. Huit expériences en phase aigüe ont étés menées sur des chiens pour vérifier la réponse de la vessie et du sphincter urétral externe à la stratégie de stimulation proposée. Le blocage à haute-fréquence (1 kHz) combiné à la stimulation basse-fréquence (30 Hz), a augmenté la différence de pression intra-vésicale/intra-urétrale moyenne jusqu'à 53 cmH2O et a réduit la pression intra-urétrale moyenne jusqu'à hauteur de 86 % relativement au niveau de référence. Dans l’objectif de tester la stratégie de neurostimulation proposée avec des expériences animales en phase chronique, un dispositif de neurostimulation implantable est requis. Un prototype discret implémentant cette stratégie de stimulation a été réalisé en utilisant uniquement des composants discrets disponibles commercialement. Ce prototype est capable de générer des impulsions à une fréquence aussi basse que 18 Hz tout en générant simultanément une forme d’onde alternative à une fréquence aussi haute que 8.6 kHz, et ce sur de multiples canaux. Lorsque tous les étages de stimulation et leurs différentes sorties sont activés avec des fréquences d’impulsions (2 mA, 217 μs) et de sinusoïdes de 30 Hz et 1 kHz respectivement, la consommation de puissance totale est autour de 4.5 mA (rms). Avec 50 mW de puissance inductive disponible par exemple et 4.5 mA de consommation de courant, le régulateur haute-tension peut être réglé à 10 V permettant ainsi une stimulation de 2 mA avec une impédance nerf-électrode de 4.4 kΩ. Le nombre effectif de sorties activées et le maximum réalisable des paramètres de stimulation sont limités par l’énergie disponible fournie par le lien inductif et l’impédance des interfaces nerf-électrode. Cependant, une plus grande intégration du neurostimulateur devient de plus en plus nécessaire à des fins de miniaturisation, de réduction de consommation de puissance, et d’augmentation du nombre de canaux de stimulation. Comme première étape vers une intégration totale, nous présentons la conception d’un neurostimulateur hautement intégré et qui peut être assemblé sur un circuit imprimé de 21 mm de diamètre. Le prototype est basé sur trois circuits intégrés, dédiés et fabriqués en technologie CMOS haute-tension, ainsi qu’un FPGA miniature à faible puissance et disponible commercialement. En utilisant une approche basée sur un abaisseur de tension, où la tension induite est laissée libre jusqu’à 20 V, l’étage d’entrée de récupération de puissance inductive et de données est totalement intégré.----------ABSTRACT Spinal cord injury (SCI) is a devastating condition medically and socially. For the population of USA only, the incidence is around 10 000 new cases per year. SCI leads to different degrees of dysfunction of the lower urinary tract due to a large variety of possible lesions. With a complete lesion, there is a complete loss of sensory and motor control below the level of lesion. An incomplete lesion implies that some sensory and/or motor activity is still present. Most patients with suprasacral SCI suffer from detrusor over-activity (DO) and detrusor sphincter dyssynergia (DSD). DSD leads to high intravesical pressure, high residual urine, urinary tract infection, and deterioration of the upper urinary tract. In this context, neurostimulation is one of the most promising techniques for bladder rehabilitation in SCI patients. The only commercialized implantable neurostimulator aiming for improved micturition and having obtained satisfactory results requires rhizotomy to reduce DSD. However, rhizotomy is irreversible and may abolish sexual and defecation reflexes as well as sacral sensations, if still present in case of incomplete SCI. In order to avoid rhizotomy, we propose a new multisite stimulation strategy applied to sacral roots, and based on nerve conduction blockade using high-frequency stimulation as an alternative to rhizotomy. This approach would allow a better micturition by increasing bladder contraction selectively and decreasing dyssynergia. Eight acute dog experiments were carried out to verify the bladder and the external urethral sphincter responses to the proposed stimulation strategy. High-frequency blockade (1 kHz) combined with low-frequency stimulation (30 Hz) increased the average intravesical-intraurethral pressure difference up to 53 cmH2O and reduced the average intraurethral pressure with respect to baseline by up to 86 %. To test the proposed neurostimulation strategy during chronic animal experiments, an implantable neurostimulateur is required. A discrete prototype implementing the proposed stimulation strategy has been designed using commercially available discrete components. This prototype is capable of generating a low frequency pulse waveform as low as 18 Hz with a simultaneous high frequency alternating waveform as high as 8.6 kHz, and that over different and multiple channels

On-chip Electro-static Discharge (esd) Protection For Radio-frequency Integrated Circuits

Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device\u27s performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. iv The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT\u27s snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Postsnapback saturation is caused by temperature-induced mobility degradation due to IIIV compound semiconductor materials\u27 poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT\u27s InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancementmode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ( \u3e 5.2 A It2) under HBM. v Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR\u27s impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. vi Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D