Investigating the DPA-Resistance Property of Charge Recovery Logics

The threat of DPA attacks is of crucial importance when designing cryptographic hardware. As a result, several DPA countermeasures at the cell level have been proposed in the last years, but none of them offers perfect protection against DPA attacks. Moreover, all of these DPA-resistant logic styles increase the power consumption and the area consumption significantly. On the other hand, there are some logic styles which provide less power dissipation (so called charge recovery logic) that can be considered as a DPA countermeasure. In this article we examine them from the DPA-resistance point of view. As an example of charge recovery logic styles, 2N-2N2P is evaluated. It is shown that the usage of this logic style leads to an improvement of the DPA-resistance and at the same time reduces the energy consumption which make it especially suitable for pervasive devices. In fact, it is the first time that a proposed DPA-resistant logic style consumes less power than the corresponding standard CMOS circuit

Single-Rail Adiabatic Logic for Energy-Efficient and CPA-Resistant Cryptographic Circuit in Low-Frequency Medical Devices

Designing energy-efficient and secure cryptographic circuits in low-frequency medical devices are challenging due to low-energy requirements. Also, the conventional CMOS logic-based cryptographic circuits solutions in medical devices can be vulnerable to side-channel attacks (e.g. correlation power analysis (CPA)). In this article, we explored single-rail Clocked CMOS Adiabatic Logic (CCAL) to design an energy-efficient and secure cryptographic circuit for low-frequency medical devices. The performance of the CCAL logic-based circuits was checked with a power clock generator (2N2P-PCG) integrated into the design for the frequency range of 50 kHz to 250 kHz. The CCAL logic gates show an average of approximately 48% energy-saving and more than 95% improvement in security metrics performance compared to its CMOS logic gate counterparts. Further, the CCAL based circuits are also compared for energy-saving performance against dual-rail adiabatic logic, 2-EE-SPFAL, and 2-SPGAL. The adiabatic CCAL gates save on an average of 55% energy saving compared to 2-EE-SPFAL and 2-SPGAL over the frequency range of 50 kHz to 250 kHz. To check the efficacy of CCAL to design a larger cryptographic circuit, we implemented a case-study design of a Substitution-box (S-box) of popular lightweight PRESENT-80 encryption. The case-study implementation (2N2P-PCG integrated into the design) using CCAL shows more than 95% energy saving compared to CMOS for the frequency 50 kHz to 125 kHz and around 60% energy saving at frequency 250 kHz. At 250 kHz, compared to the dual-rail adiabatic designs of S-box based on 2-EE-SPFAL and 2-SPGAL, the CCAL based S-box shows 32.67% and 11.21% of energy savings, respectively. Additionally, the CCAL logic gate structure requires a lesser number of transistors compared to dual-rail adiabatic logic. The case-study implementation using CCAL saves 45.74% and 34.88% transistor counts compared to 2-EE-SPFAL and 2-SPGAL. The article also presents the effect of varying tank capacitance in 2N2P-PCG over energy efficiency and security performance. The CCAL based case-study was also subjected against CPA. The CCAL-based S-box case study successfully protects the revelation of the encryption key against the CPA attack, However, the key was revealed in CMOS-based case-study implementation

Side Channel Information Leakage: Design and Implementation of Hardware Countermeasure

Deployment of Dynamic Differential Logics (DDL) appears to be a promising choice for providing resistance against leakage of side channel information. However, the resistance provided by these logics is too costly for widespread area-constrained applications. Implementation of a secure DDL-based countermeasure also requires a complex layout methodology for balancing the load at the differential outputs. This thesis, unlike previous logic level approaches, presents a novel exploitation of static and single-ended logic for designing the side channel countermeasure. The proposed technique is used in the implementation of a protected crypto core consisting of the AES “AddRoundKey” and “SubByte” transformation. The test chip including the protected and unprotected crypto cores is fabricated in 180nm CMOS technology. A correlation analysis on the unprotected core results in revealing the key at the output of the combinational networks and the registers. The quality of the measurements is further improved by introducing an enhanced data capturing method that inserts a minimum power consuming input as a reference vector. In comparison, no key-related information is leaked from the protected core even with an order of magnitude increase in the number of averaged traces. For the first time, fabricated chip results are used to validate a new logic level side channel countermeasure that offers lower area and reduced circuit design complexity compared to the DDL-based countermeasures. This thesis also provides insight into the side channel vulnerability of cryptosystems in sub-90nm CMOS technology nodes. In particular, data dependency of leakage power is analyzed. The number of traces to disclose the key is seen to decrease by 35% from 90nm to 45nm CMOS technology nodes. Analysis shows that the temperature dependency of the subthreshold leakage has an important role in increasing the ability to attack future nanoscale crypto cores. For the first time, the effectiveness of a circuit-based leakage reduction technique is examined for side channel security. This investigation demonstrates that high threshold voltage transistor assignment improves resistance against information leakage. The analysis initiated in this thesis is crucial for rolling out the guidelines of side channel security for the next generation of Cryptosystem.1 yea

Designing Novel Hardware Security Primitives for Smart Computing Devices

Smart computing devices are miniaturized electronics devices that can sense their surroundings, communicate, and share information autonomously with other devices to work cohesively. Smart devices have played a major role in improving quality of the life and boosting the global economy. They are ubiquitously present, smart home, smart city, smart girds, industry, healthcare, controlling the hazardous environment, and military, etc. However, we have witnessed an exponential rise in potential threat vectors and physical attacks in recent years. The conventional software-based security approaches are not suitable in the smart computing device, therefore, hardware-enabled security solutions have emerged as an attractive choice. Developing hardware security primitives, such as True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) from electrical properties of the sensor could be a novel research direction. Secondly, the Lightweight Cryptographic (LWC) ciphers used in smart computing devices are found vulnerable against Correlation Power Analysis (CPA) attack. The CPA performs statistical analysis of the power consumption of the cryptographic core and reveals the encryption key. The countermeasure against CPA results in an increase in energy consumption, therefore, they are not suitable for battery operated smart computing devices. The primary goal of this dissertation is to develop novel hardware security primitives from existing sensors and energy-efficient LWC circuit implementation with CPA resilience. To achieve these. we focus on developing TRNG and PUF from existing photoresistor and photovoltaic solar cell sensors in smart devices Further, we explored energy recovery computing (also known as adiabatic computing) circuit design technique that reduces the energy consumption compared to baseline CMOS logic design and same time increasing CPA resilience in low-frequency applications, e.g. wearable fitness gadgets, hearing aid and biomedical instruments. The first contribution of this dissertation is to develop a TRNG prototype from the uncertainty present in photoresistor sensors. The existing sensor-based TRNGs suffer a low random bit generation rate, therefore, are not suitable in real-time applications. The proposed prototype has an average random bit generation rate of 8 kbps, 32 times higher than the existing sensor-based TRNG. The proposed lightweight scrambling method results in random bit entropy close to ideal value 1. The proposed TRNG prototype passes all 15 statistical tests of the National Institute of Standards and Technology (NIST) Statistical Test Suite with quality performance. The second contribution of this dissertation is to develop an integrated TRNG-PUF designed using photovoltaic solar cell sensors. The TRNG and PUF are mutually independent in the way they are designed, therefore, integrating them as one architecture can be beneficial in resource-constrained computing devices. We propose a novel histogram-based technique to segregate photovoltaic solar cell sensor response suitable for TRNG and PUF respectively. The proposed prototype archives approximately 34\% improvement in TRNG output. The proposed prototype achieves an average of 92.13\% reliability and 50.91\% uniformity performance in PUF response. The proposed sensor-based hardware security primitives do not require additional interfacing hardware. Therefore, they can be ported as a software update on existing photoresistor and photovoltaic sensor-based devices. Furthermore, the sensor-based design approach can identify physically tempered and faulty sensor nodes during authentication as their response bit differs. The third contribution is towards the development of a novel 2-phase sinusoidal clocking implementation, 2-SPGAL for existing Symmetric Pass Gate Adiabatic Logic (SPGAL). The proposed 2-SPGAL logic-based LWC cipher PRESENT shows an average of 49.34\% energy saving compared to baseline CMOS logic implementation. Furthermore, the 2-SPGAL prototype has an average of 22.76\% better energy saving compared to 2-EE-SPFAL (2-phase Energy-Efficient-Secure Positive Feedback Adiabatic Logic). The proposed 2-SPGAL was tested for energy-efficiency performance for the frequency range of 50 kHz to 250 kHz, used in healthcare gadgets and biomedical instruments. The proposed 2-SPGAL based design saves 16.78\% transistor count compared to 2-EE-SPFAL counterpart. The final contribution is to explore Clocked CMOS Adiabatic Logic (CCAL) to design a cryptographic circuit. Previously proposed 2-SPGAL and 2-EE-SPFAL uses two complementary pairs of the transistor evaluation network, thus resulting in a higher transistor count compared to the CMOS counterpart. The CCAL structure is very similar to CMOS and unlike 2-SPGAL and 2-EE-SPFAL, it does not require discharge circuitry to improve security performance. The case-study implementation LWC cipher PRESENT S-Box using CCAL results into 45.74\% and 34.88\% transistor count saving compared to 2-EE-SPFAL and 2-SPGAL counterpart. Furthermore, the case-study implementation using CCAL shows more than 95\% energy saving compared to CMOS logic at frequency range 50 kHz to 125 kHz, and approximately 60\% energy saving at frequency 250 kHz. The case study also shows 32.67\% and 11.21\% more energy saving compared to 2-EE-SPFAL and 2-SPGAL respectively at frequency 250 kHz. We also show that 200 fF of tank capacitor in the clock generator circuit results in optimum energy and security performance in CCAL

ASSESSING AND IMPROVING THE RELIABILITY AND SECURITY OF CIRCUITS AFFECTED BY NATURAL AND INTENTIONAL FAULTS

The reliability and security vulnerability of modern electronic systems have emerged as concerns due to the increasing natural and intentional interferences. Radiation of high-energy charged particles generated from space environment or packaging materials on the substrate of integrated circuits results in natural faults. As the technology scales down, factors such as critical charge, voltage supply, and frequency change tremendously that increase the sensitivity of integrated circuits to natural faults even for systems operating at sea level. An attacker is able to simulate the impact of natural faults and compromise the circuit or cause denial of service. Therefore, instead of utilizing different approaches to counteract the effect of natural and intentional faults, a unified countermeasure is introduced. The unified countermeasure thwarts the impact of both reliability and security threats without paying the price of more area overhead, power consumption, and required time. This thesis first proposes a systematic analysis method to assess the probability of natural faults propagating the circuit and eventually being latched. The second part of this work focuses on the methods to thwart the impact of intentional faults in cryptosystems. We exploit a power-based side-channel analysis method to analyze the effect of the existing fault detection methods for natural faults on fault attack. Countermeasures for different security threats on cryptosystems are investigated separately. Furthermore, a new micro-architecture is proposed to thwart the combination of fault attacks and side-channel attacks, reducing the fault bypass rate and slowing down the key retrieval speed. The third contribution of this thesis is a unified countermeasure to thwart the impact of both natural faults and attacks. The unified countermeasure utilizes dynamically alternated multiple generator polynomials for the cyclic redundancy check (CRC) codec to resist the reverse engineering attack

Acts of contention: local practices and dynamics of negotiated statebuilding in Bosnia and Herzegovina 1995-2010

The thesis is concerned with local practices that seek to contest international statebuilding measures. This line of inquiry stems from the need to generate knowledge on the ways in which international statebuilding is mediated and re-negotiated in local spaces. Rather than focusing on the much-analyzed hidden/everyday forms of resistance, the objective of the analysis is to understand the parallel, disruptive practices that directly challenge the international statebuilding project. These particular forms of contention are important as they explicitly engage with the coercive power of international statebuilding. Through the case study of post-Dayton Bosnia and Herzegovina, the thesis aims to generate an account of local contention and dynamics between domestic and international actors that is attentive to both material and non-material domains and practices. In doing so, the analysis identifies a range of contentious acts in the institutional, discursive and symbolic domains. While administrative practices slow down and block decision-making at the institutions of governance, local actors frequently deploy discursive strategies to destabilize and de-legitimize, or in some cases to co-opt, international statebuilding. They employ symbols and symbolic practices to contest the internationally-led cultural reconstruction efforts. It is argued that these disruptive techniques and the ensuing interactions translate into conflictual and symbiotic dynamic between internal and external actors. Although the interactions between internal and external actors frequently result in conflict, a closer look at the dynamic reveals a mutual dependency whereby the contentious activities of local actors and coercive statebuilding measures of the international officials maintain one another. The thesis makes a conceptual and empirical contribution to the analysis and understanding of the hybrid nature of post-conflict statebuilding. It begins developing the notion of contention and a set of mechanisms derived from contentious politics scholarship as a way to capture and trace local practices challenging internationally-led statebuilding measures. Empirically the study adds to our knowledge of local agency in societies emerging from conflicts

Essays on China’s Political Organization and Political Economic Institutions

The present dissertation is a compilation of three individual papers, and an introduction chapter. While the introduction lays out the theoretic backdrop of the project as a whole, the papers represent interventions into three specific dimensions of China’s Party-state order: structural organizational issues, decision-making institutions, and political economic dynamics. These three dimensions are presented as aspects of the same political organizational order, a Party-state order assembled around the hegemony of the Communist Party of China’s (CPC), conceptualized in the introduction using a Gramsci-inspired theory of the state. Employing a historical institutional approach, the three papers engage with specific strands of literatures of China Studies in a conceptual and theoretic manner, while also contributing with empirical findings. They discuss the concept of Fragmented Authoritarianism (FA), the organization and institutionalization of Leading Small Groups, and the social embeddedness of state-owned enterprise (SOE). FA has been an influential concept to explain structural issues of China’s bureaucracy, and with China’s energy administration as example, I review its value as a theoretic notion today, 30 years after its inception. Discussing the growing importance of Leading Small Groups, the second paper addresses some of the institutional “fixes” to decisionmaking and policy coordination, which have evolved in response to structural fault-lines described in the FA paper. The third paper takes the dissertation into the political economic dimension of the Party-state order, providing a case study of how China National Petroleum Corporation, a central, state-owned and CPC led SOE, is organizationally rooted in its local operations, remaining institutionally embedded in local society through its legacy as a socialist work unit (danwei). Using Polanyi’s concept of embeddedness, the paper reveals how SOEs are split into two tiers each tasked with the respective objectives of economic development and political stability, and thus as Party-state organizations are used to flexibly support CPC hegemony

Development and Validation of a Computational Tool for Fusion Reactors\u27 System Analysis

On the roadmap to fusion energy the development and the operation of a demonstration power plant (DEMO) is the next step after ITER, a key facility currently devoted to the exploration of the physics aspects for self-sustained fusion plasmas with sizes and fusion power comparable to those attended in fusion power plants (FPP). Fusion systems codes are essential computational tools aimed to simulate the physics and the engineering features of a FPP. The main objective of a system code is to find one (or more) reactor configurations which simultaneously comply with physics operational limits, engineering constraints and net electric output requirements. As such simulation tools need to scope many design solutions over a large parameter phase space, they rely on rather basic physics and engineering models (mostly at zero or one-dimensional level) and on a relatively large number of input specifications. Within the conceptual design of a FPP, systems codes are interfaced to the detailed transport codes and engineering platforms, which operate in much larger time scales. To fill the gap between systems and the detailed transport and engineering codes the high-fidelity system/design tool MIRA (Modular Integrated Reactor Analysis) has been developed. MIRA relies on a modular structure and provides a refined FPP system analysis, with the primary goal of generating a more robust plant baseline. It incorporates into a unique computing environment a mathematical algorithm for the utmost tokamak fusion problems, including two-dimensional plasma magnetic equilibrium and core physics, transport of neutron and photon radiations emitted from the plasma and electromagnetic and engineering characterization of the toroidal field (TF) and poloidal field (PF) field coil systems. Most of the implemented modules rely on higher spatial resolution compared to presently available system codes, such as PROCESS. The multiphysics MIRA approach has been applied to the DEMO 2015 baseline, generated by means of the PROCESS system code. The analysis has been carried out by taking an identical set of input assumptions and requirements (e.g. same fusion power, major radius and aspect ratio) and observing the response on certain figures of merit. This verification study has featured the violation of some constraining conditions imposed on plasma safety factor, TF ripple and plasma burn time. The DEMO 2015 baseline has been found not in line with all the imposed requirements and constraints, hence necessitates a set of active measures on some of the input parameters. Such measures have been reported in form of parameter scans, where three variables have been identified, such as plasma internal inductance, blanket breeding zone inboard thickness and vacuum vessel/TF coil gap radial outboard width. The addressed sensitivity analyses have shown non-trivial inter-parametric dependencies, never explored in fusion system analyses. For instance, large influences of the plasma internal inductance on safety factor, plasma shape, density and temperature features, peak divertor flux and plasma burn time have been observed. Moreover, an optimal overall breeding blanket + TF coil inboard width has been observed with respect to the maximization of the plasma burn time, representing a meeting point between neutronic tritium breeding and technological limits in central solenoid and TF coils superconducting cables. These outcomes have inspired important changes in the way of designing a tokamak reactor like DEMO, where more extended analyses of the key physics and engineering aspects of the reactor can speed up and improve the design process of a FPP