Performance analysis of error detection and correction code for wireless sensor networks

Recent advances in wireless communications and electronics have enabled the development of low-cost, low-power, self-organizational, multifunctional wireless sensor networks. Wireless sensor networks can be applied to a wide range of application areas including heath, military and homeland security, environment, industry and commercial, and home. A typical wireless sensor network consists of one or more sink nodes and a large number of sensor nodes scattered in a sensor field. Each of these sensor nodes is capable to collect the data and relay the data back to the sink through a multi-hop architecture. The key challenge in sensor networks is to overcome the energy constraint since each sensor node has limited power. Hence, it is important to minimize the energy used to transmit packets over wireless links; The data transmitted from the sensor nodes are vulnerable to be corrupted by errors induced by noisy channels and other factors. Hence it is necessary to provide a proper error control scheme to reduce the bit error rate (BER) to a desired level without sacrificing other performance. Energy required for error control code has a direct impact on battery power consumption. Since high error rates are inevitable in the wireless environment, energy efficient error detection and correction scheme is vital in wireless sensor networks. However, in the literature, limited work has been focused on the study of energy efficient error control scheme; This thesis is focused on energy-efficient error detection and correction schemes for wireless sensor networks. (Abstract shortened by UMI.)

낸드 플래시 메모리 오류 정정을 위한 병렬 BCH 복호기의 최적 설계

In this work, we have developed a parallel BCH decoder for multi-level cell NAND flash memory. The decoder is designed to require minimum chip area as well as minimum power consumption for NAND flash memory applications. To achieve this goal, the parallle factor of each functional block is determined by using design exploitation techniques.본 논문은 지식경제부 출연금으로 ETRI, 시스템반도체 산업진흥센터에서 수행한 IT SoC 핵심설계인력양성사업의 연구결과입니다

Performance of FEC codes over AWGN channel for efficient use in Polymer Optical Fiber links

Volume 1 Issue 7 (September 2013

Efficient ASIC Architectures for Low Latency Niederreiter Decryption

Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available quantum-resistant systems, the Niederreiter cryptosystem is positioned as a conservative choice with strong security guarantees. As a code-based cryptosystem, the Niederreiter system enables high performance operations and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Niederreiter operations. Therefore, the present work targets the design, implementation and optimization of tailored archi- tectures for low latency Niederreiter decryption. Two architectures utilizing different decoding algorithms are proposed and implemented using a 22nm FDSOI CMOS technology node. One of these optimized architectures improves the decryption latency by 27% compared to a state-of-the-art reference and requires at the same time only 25% of the area

On the Complexity of Decoders for Goppa Codes

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / DAAB-07-72-C-0259National Science Foundation / GK-2487

Alternant and BCH codes over certain rings

Alternant codes over arbitrary finite commutative local rings with identity are constructed in terms of parity-check matrices. The derivation is based on the factorization of x s - 1 over the unit group of an appropriate extension of the finite ring. An efficient decoding procedure which makes use of the modified Berlekamp-Massey algorithm to correct errors and erasures is presented. Furthermore, we address the construction of BCH codes over Zm under Lee metric.23324

FPGA-based architectures for next generation communications networks

This engineering doctorate concerns the application of Field Programmable Gate Array (FPGA) technology to some of the challenges faced in the design of next generation communications networks. The growth and convergence of such networks has fuelled demand for higher bandwidth systems, and a requirement to support a diverse range of payloads across the network span. The research which follows focuses on the development of FPGA-based architectures for two important paradigms in contemporary networking - Forward Error Correction and Packet Classification. The work seeks to combine analysis of the underlying algorithms and mathematical techniques which drive these applications, with an informed approach to the design of efficient FPGA-based circuits