Using Embedded Xinu and the Raspberry Pi 3 to Teach Operating Systems

Multicore processors have become the standard in modern computing platforms. Such complex hardware enables faster execution of the programs it runs, but this is only true if its programmer has the knowledge and ability to make it so. Thus, there is a great need to prepare computing students by establishing robust educational tools. Existing tools often include abstract learning environments such as a virtual machine. While such platforms are widely available and convenient, they are unable to expose students to concurrency on real hardware.This paper presents multicore Embedded Xinu, an educational operating system used to teach concurrency concepts at the university level. The latest port of Embedded Xinu to the four-core, ARM-based Raspberry Pi 3 B+ enabled an operating systems curriculum in which students build their own concurrency-oriented kernel and execute it on a real machine. Assignments that have been run in the course include concepts of synchronization, scheduling, and memory allocation on a multicore platform. Upon completing the course, students are capable of solving problems commonly found in the field of parallel computing

Tareador: a tool to unveil parallelization strategies at undergraduate level

This paper presents a methodology and framework designed to assist students in the process of finding appropriate task decomposition strategies for their sequential program, as well as identifying bottlenecks in the later execution of the parallel program. One of the main components of this framework is Tareador, which provides a simple API to specify potential task decomposition strategies for a sequential program. Once the student proposes how to break the sequential code into tasks, Tareador 1) provides information about the dependences between tasks that should be honored when implementing that task decomposition using a parallel programming model; and 2) estimates the potential parallelism that could be achieved in an ideal parallel architecture with infinite processors; and 3) sim- ulates the parallel execution on an ideal architecture estimating the potential speed–up that could be achieved on a number of processors. The pedagogical style of the methodology is currently applied to teach parallelism in a third-year compulsory subject in the Bachelor Degree in Informatics Engineering at the Barcelona School of Informatics of the Universitat Politècnica de Catalunya (UPC) - BarcelonaTech.Peer ReviewedPostprint (published version

Software Engineering for Science

Software Engineering for Science provides an in-depth collection of peer-reviewed chapters that describe experiences with applying software engineering practices to the development of scientific software. It provides a better understanding of how software engineering is and should be practiced, and which software engineering practices are effective for scientific software. The book starts with a detailed overview of the Scientific Software Lifecycle, and a general overview of the scientific software development process. It highlights key issues commonly arising during scientific software development, as well as solutions to these problems. The second part of the book provides examples of the use of testing in scientific software development, including key issues and challenges. The chapters then describe solutions and case studies aimed at applying testing to scientific software development efforts. The final part of the book provides examples of applying software engineering techniques to scientific software, including not only computational modeling, but also software for data management and analysis. The authors describe their experiences and lessons learned from developing complex scientific software in different domains

EASYPAP: a Framework for Learning Parallel Programming

This paper presents EASYPAP, an easy-to-use programming environment designed to help students to learn parallel programming. EASYPAP features a wide range of 2D computation kernels that the students are invited to parallelize using Pthreads, OpenMP, OpenCL or MPI. Execution of kernels can be interactively visualized, and powerful monitoring tools allow students to observe both the scheduling of computations and the assignment of 2D tiles to threads/processes. By focusing on algorithms and data distribution, students can experiment with diverse code variants and tune multiple parameters, resulting in richer problem exploration and faster progress towards efficient solutions. We present selected lab assignments which illustrate how EASYPAP improves the way students explore parallel programming

Celebrating Faculty Scholarship: Bibliography - 2011

A bibliography of faculty publications submitted for inclusion in the fourth annual \u27Celebrating Faculty Scholarship\u27 event sponsored by Loyola University Libraries. The event, which took place on October 24, 2012 in the Richard J. Klarchek Information Commons on the university\u27s Lake Shore Campus, featured articles, books, creative works, and other materials authored by Loyola University Chicago faculty in 2011

Celebrating Faculty Scholarship: Bibliography - 2013

A bibliography of faculty publications submitted for inclusion in the fifth annual \u27Celebrating Faculty Scholarship\u27 event sponsored by Loyola University Libraries. The event, which took place on October 21, 2014 in the Richard J. Klarchek Information Commons on the university\u27s Lake Shore Campus, featured articles, books, creative works, and other materials authored by Loyola University Chicago faculty in 2013

Feasibility Study of Scaling an XMT Many-Core

The reason for recent focus on communication avoidance is that high rates of data movement become infeasible due to excessive power dissipation. However, shifting the responsibility of minimizing data movement to the parallel algorithm designer comes at significant costs to programmer’s productivity, as well as: (i) reduced speedups and (ii) the risk of repelling application developers from adopting parallelism. The UMD Explicit Multi-Threading (XMT) framework has demonstrated advantages on ease of parallel programming through its support of PRAM-like programming, combined with strong, often unprecedented speedups. Such programming and speedups involve considerable data movement between processors and shared memory. Another reason that XMT is a good test case for a study of data movement is that XMT permits isolation and direct study of most of its data movement (and its power dissipation). Our new results demonstrate that an XMT single-chip many-core processor with tens of thousands of cores and a high throughput network on chip is thermally feasible, though at some cost. This leads to a perhaps game-changing outcome: instead of imposing upfront strict restrictions on data movement, as advocated in a recent report from the National Academies, opt for due diligence that accounts for the full impact on cost. For example, does the increased cost due to communication avoidance (including programmer’s productivity, reduced speedups and desertion risk) indeed offset the cost of the solution we present? More specifically, we investigate in this paper the design of an XMT many-core for 3D VLSI with microfluidic cooling. We used state-of-the-art simulation tools to model the power and thermal properties of such an architecture with 8k to 64k lightweight cores, requiring between 2 and 8 silicon layers. Inter-chip communication using silicon compatible photonics is also considered. We found that, with the use of microfluidic cooling, power dissipation becomes a cost issue rather than a feasibility constraint. Robustness of the results is also discussed.DARPA, NSF, NI

Education Systems Around the World

This book, "Education Systems Around the World", is a collection of reviewed and relevant research chapters that offer a comprehensive overview of recent developments in the field of social sciences and humanities. The book comprises single chapters authored by various researchers and edited by an expert active in the field of social studies and humanities. All chapters are unique but are united under a common research study topic. This publication aims to provide a thorough overview of the latest research efforts by international authors on social studies and humanities, and open new possible research paths for further novel developments

A NOVEL LINEAR DIOPHANTINE EQUATION-BAESD LOW DIAMETER STRUCTURED PEER-TO-PEER NETWORK

This research focuses on introducing a novel concept to design a scalable, hierarchical interest-based overlay Peer-to-Peer (P2P) system. We have used Linear Diophantine Equation (LDE) as the mathematical base to realize the architecture. Note that all existing structured approaches use Distributed Hash Tables (DHT) and Secure Hash Algorithm (SHA) to realize their architectures. Use of LDE in designing P2P architecture is a completely new idea; it does not exist in the literature to the best of our knowledge. We have shown how the proposed LDE-based architecture outperforms some of the most well established existing architecture. We have proposed multiple effective data query algorithms considering different circumstances, and their time complexities are bounded by (2+ r/2) only; r is the number of distinct resources. Our alternative lookup scheme needs only constant number of overlay hops and constant number of message exchanges that can outperform DHT-based P2P systems. Moreover, in our architecture, peers are able to possess multiple distinct resources. A convincing solution to handle the problem of churn has been offered. We have shown that our presented approach performs lookup queries efficiently and consistently even in presence of churn. In addition, we have shown that our design is resilient to fault tolerance in the event of peers crashing and leaving. Furthermore, we have proposed two algorithms to response to one of the principal requests of P2P applications’ users, which is to preserve the anonymity and security of the resource requester and the responder while providing the same light-weighted data lookup