Analog Circuits in Ultra-Deep-Submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

Adaptive differential amplitude pulse-position modulation technique (DAPPM) using fuzzy logic for optical wireless communication channels

In the past few years, people have become increasingly demanding for high transmission rate, using high-speed data transfer rate, the number of user increased every year, therefore the high-speed optical wireless communication link have become more popular. Optical wireless communication has the potential for extremely high data rates of up to tens of Gigabits per second (Gb/s). An optical wireless channel is usually a non-directed link which can be categorized as either line-of-sight (LOS) or diffuses. Modulation techniques have attracted increasing attention in optical wireless communication, therefore in this project; a hybrid modulation technique named Differential Amplitude Pulse-Position Modulation (DAPPM) is proposed to improve the channel immunity by utilizing optimized modulation to channel. The average symbol length, unit transmission rate, channel capacity, peak-to-average power ratio (PAPR), transmission capacity, bandwidth requirement and power requirement of the DAPPM were determined and compared with other modulation schemes such as On-Off Key (OOK), Pulse-Amplitude Modulation (PAM), Pulse-Position Modulation (PPM), Differential Pulse-Position Modulation (DPPM), and Multilevel Digital Pulse Interval Modulation (MDPIM). Simulation result shows that DAPPM gives better bandwidth and power efficiency depending on the number of amplitude level (A) and the maximum length (L) of a symbol. In addition, the fuzzy logic module is developed to assist the adaptation process of differential amplitude pulse-position modulation. Mamdani fuzzy logic method is used in which the decisions made by the system will be approaching to what would be decided by the user in the real world

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0,18 µm CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles have been used (gamma rays, X-rays, protons and neutrons) to irradiate the studied devices. Both total ionizing dose (TID) and displacement damage effects are reported. The most sensitive parameter is still the dark current but some quantum eficiency and MOSFET characteristics changes were also observed at higher dose than those of interest for space applications. In all these degradations, the trench isolations play an important role. The consequences on radiation testing for space applications and radiation-hardening-by-design techniques are also discussed

A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 100 kGy (SiO/sub 2/), and they do not degrade after irradiation. (15 refs)

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn. (16 refs)

Monolithic Pixel Sensors in Deep-Submicron SOI Technology with Analog and Digital Pixels

This paper presents the design and test results of a prototype monolithic pixel sensor manufactured in deep-submicron fully-depleted Silicon-On-Insulator (SOI) CMOS technology. In the SOI technology, a thin layer of integrated electronics is insulated from a (high-resistivity) silicon substrate by a buried oxide. Vias etched through the oxide allow to contact the substrate from the electronics layer, so that pixel implants can be created and a reverse bias can be applied. The prototype chip, manufactured in OKI 0.15 micron SOI process, features both analog and digital pixels on a 10 micron pitch. Results of tests performed with infrared laser and 1.35 GeV electrons and a first assessment of the effect of ionising and non-ionising doses are discussed.Comment: 5 pages, 7 figures, submitted to Nuclear Instruments and Methods