A multiprocessor based packet-switch: performance analysis of the communication infrastructure

The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the Network-On-Chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found

Quarc: an architecture for efficient on-chip communication

The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems. Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm. By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence. To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of the building blocks of the architecture, including topology, router and network interface. The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture. Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Emulator- und kostenbasierte Analyse von Network-on-Chip

Die Komplexität der Kommunikation auf aktuellen und zukünftigen Multi-Kern System on Chip ist mit gängigen Kommunikationsarchitekturen wie Bussen oder Punkt-zu-Punkt Verbindungen kaum zu beherrschen. Network-on-Chip (NoC) stellen eine mögliche Lösung dieses Problems dar. Im Rahmen dieser Arbeit wurde ein modulares und parametrisierbares Network-on-Chip entwickelt. Dies unterstütze eine Vielzahl von NoC-Parametern wie zum Beispiel Topologie, Routing Algorithmus und Vermittlungstechnik. Die erstellte VHDL Bibliothek für NoC ermöglicht die automatische Generierung von NoC-Beschreibungen in VHDL. Für die Untersuchung der Performance, Fläche und Verlustleistung der modellierten NoC wurden exemplarische VLSI-Implementierungen der NoC-Komponenten mit Hilfe von Standardzellen erstellt. Zur Reduzierung der Kosten und Steigerung der Performance sind physikalisch optimierte Kernkomponenten in Kombination mit Standardzellen verwendet worden. Dies reduziert die Kosten der NoC-Implementierungen signifikant wobei die Parametrisierbarkeit erhalten bleibt. Die Kosten für die NoC-Komponenten in Abhängigkeit der NoC-Parameter wurden mit mathematischen Modellen beschrieben. Diese Modelle erlauben die Abschätzung der zu erwartenden Kosten schon in frühen Entwurfsphasen. Neben den Kosten, die durch ein NoC verursacht werden, ist die Bestimmung der Performance eines NoCs wichtig. Es wurden verschiedene Techniken (z.B. Simulation auf unterschiedlichen Abstraktionsebenen, Emulation auf einem FPGA) implementiert, um die Performance von NoC zu bestimmen. Die Erweiterung der NoC-Beschreibung um weitere Bibliotheken zur Simulation mit SystemC und Colored-Petri-Nets, einer Emulation auf einem FPGA und der statischen Analyse ermöglichten einen Vergleich und eine Bewertung dieser Techniken. Die Analyse-Techniken wurden den unterschiedlichen Phasen im Entwurfs-prozess von NoC zugeordnet. Durch die Vielzahl an NoC-Parametern ist der Entwurf eines optimalen NoC sehr komplex und aufwändig. Die Erkenntnisse dieser Arbeit wurden in einer Entwurfsmethodik zusammengeführt. Dieses Spiral-Modell ermöglicht eine effiziente, automatisierte Implementierung von NoC. Bei dem Vergleich der implementierten NoC-Komponenten mit Beispielen aus der Literatur konnte die Effizienz und Leistungsfähigkeit gezeigt werden. Für Anwendungsbeispiele aus der Literatur und zufälligen Datenverkehr konnte der Entwurfsraum für NoC erfolgreich untersucht und jeweils Pareto-optimale NoC identifiziert werden. Die Analyse des Kommunikationsverhalten eines realen Multi-Core Prozessors mit 61 Prozessorkernen und Abbildung auf den FPGA-basierten Emulator für NoC zeigen, dass die vorgestellte Methodik grundsätzlich gut für den Entwurf und die Analyse von NoC geeignet ist

Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Integrating dataflow and non-dataflow real-time application models on multi-core platforms

Ferry Jules. Facultés des sciences. Rapports sur les travaux personnels des professeurs. In: Bulletin administratif de l'instruction publique. Tome 24 n°465, 1881. pp. 529-531