Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Advanced flight computer. Special study

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated

Silicon optical modulators

Optical technology is poised to revolutionise short reach interconnects. The leading candidate technology is silicon photonics, and the workhorse of such interconnect is the optical modulator. Modulators have been improved dramatically in recent years. Most notably the bandwidth has increased from the MHz to the multi GHz regime in little more than half a decade. However, the demands of optical interconnect are significant, and many questions remain unanswered as to whether silicon can meet the required performance metrics. Minimising metrics such as the energy per bit, and device footprint, whilst maximising bandwidth and modulation depth are non trivial demands. All of this must be achieved with acceptable thermal tolerance and optical spectral width, using CMOS compatible fabrication processes. Here we discuss the techniques that have, and will, be used to implement silicon optical modulators, as well as the outlook for these devices, and the candidate solutions of the future

Analysis of terabit/second-class inter-chip parallel optoelectronic transceiver

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2010.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 89-92).Electrical copper-based interconnect has been suffering from fundamental physical loss mechanism and its current infrastructure will not be able to meet the increasing demand for data rates due to reaching the limit of the transmission bandwidth-distance product. Optical interconnect has been known as the candidate for taking over the obsolete electrical counterpart owing to the capability of transmitting data at high rates with low loss and the feasibility for parallel integration. Optoelectronic transceiver is one of the essential elements in optical interconnect system. This thesis scrutinizes a complete set of constituent technologies developed for a novel inter-chip parallel optoelectronic (OE) transceiver (known as Terabus transceiver) which is able to communicate data at the speed in the range of Terabit/second. A novel packaging hierarchy and a creative design for an optical coupling mechanism devised to bring high-level integration and high-speed performance to a final package have been analyzed: Two 4x12 arrays (each < 9 mm2) of CMOS transmitter and receiver ICs have been flip-chip bonded to a silicon carrier interposer of 1.2-cm2 size. Other two 4x12 arrays of OE devices (VCSELs and photodiodes) with comparable size are then flip-chip bonded to the corresponding CMOS arrays attached to the silicon carrier, forming the Optochip assembly. The Optochip is in interface with an Optocard by the flip-chip bonding process between the silicon carrier and an organic card patterned with 48 integrated waveguides at density of 16-channel/mm and total length of 30 cm. The 985-nm operating wavelength of the lasers allows a simple optical design with emission and illumination through arrays of relay lenses directly etched into the backside of the OE Ill-V substrate. A novel design of 45*-tilted and Au-coated mirrors fabricated in 125-ptmpitch acrylate waveguides is to perpendicularly couple the light in and out of the core of these Optocard waveguides. Per-channel performance of up to 20 Gb/s for transmitter and of up to 14 Gb/s for receiver have been realized. Lastly, the thesis has analyzed the market opportunity of the transceiver by reviewing the market situation, identifying contemporary competing technologies, assessing the market prospect and predicting the cost.by Nguyen Hoang Nguyen.M.Eng

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed