InGaAs/InP SPAD with Monolithically Integrated Zinc-Diffused Resistor

Afterpulsing and optical crosstalk are significant performance limitations for applications employing near-infrared single-photon avalanche diodes (SPADs). In this paper, we describe an InGaAs/InP SPAD with monolithically integrated resistor that is fully compatible with the planar fabrication process and provides a significant reduction of the avalanche charge and, thus, of afterpulsing and optical crosstalk. In order to have a fast SPAD reset (<50 ns), we fabricated quenching resistors ranging from 10 to 200 k\Ω, smaller than what is available in the literature. The resistor, fabricated with the zinc diffusions already used for avoiding premature edge-breakdown, promptly reduces the avalanche current to a low value ∼ 100~ μ A in less than 1 ns, while an active circuit completes the quenching and enforces a well-defined hold-off. The proposed mixed-quenching approach guarantees an avalanche charge reduction of more than 20 times compared with similar plain SPADs, enough to reduce the hold-off time down to 1 μ s. Finally, a compact single-photon counting module based on this detector and featuring 70-ps photon-timing jitter is presented

Compact CMOS active quenching/recharge circuit for SPAD arrays

Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post-layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns.Ministerio de Economía y Competitividad TEC2012-38921-C02, IPT-2011-1625-430000, IPC-20111009 CDTIJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm 2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.Ministerio de Economía y Competitividad IPT-2011-1625- 430000, IPC-20111009Office of Naval Research (USA) N00014111031

CMOS SPADs selection, modeling and characterization towards image sensors implementation

The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance

Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs

The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due to their simplicity, a way to reduce the area occupied by the integrated electronics is the use of passive quenching circuits (PQCs) instead of active (AQCs) or mixed (MQCs) ones. However, the recharge phase in PQCs is slower, so the device can be retriggered before this phase ends. This paper studies the phenomena of afterpulsing and retriggering, depending on the characteristics of the SPADs and the working conditions. In order to do that, a test chip containing SPADs of different size has been characterized in several operating environments. A mathematical model has been proposed for fitting afterpulsing phenomenon. It is shown that retriggering can be also described in terms of this model, suggesting that it is linked to carriers trapped in the shallow levels of the semiconductor and that should be taken into account when considering the total amount of afterpulsing events.Junta de Andalucía TIC 233

Realizing a Robust, Reconfigurable Active Quenching Design for Multiple Types of Single-Photon Avalanche Detectors

Most active quench circuits used for single-photon avalanche photodetectors (APDs) are designed either with discrete components which lack the flexibility of dynamically changing the control parameters, or with custom ASICs which require a long development time and high cost. As an alternative, we present a reconfigurable and robust hybrid design implemented using a System-on-Chip (SoC), which integrates both an FPGA and a microcontroller. We take advantage of the FPGA's speed and reconfiguration capabilities to vary the quench and reset parameters dynamically over a large range, thus allowing our system to operate a variety of APDs without changing the design. The microcontroller enables the remote adjustment of control parameters and calibration of APDs in the field. The ruggedized design uses components with space heritage, thus making it suitable for space-based applications in the fields of telecommunications and quantum key distribution (QKD). We demonstrate our circuit by operating a commercial APD cooled to -20{\deg}C with a deadtime of 35ns while maintaining the after-pulsing probability at close to 3%. We also showcase its versatility by operating custom-fabricated chip-scale APDs, which paves the way for automated wafer-scale characterization.Comment: 6 pages, 6 figures. arXiv admin note: substantial text overlap with arXiv:2205.0022

A universal setup for active control of a single-photon detector

The influence of bright light on a single-photon detector has been described in a number of recent publications. The impact on quantum key distribution (QKD) is important, and several hacking experiments have been tailored to fully control single-photon detectors. Special attention has been given to avoid introducing further errors into a QKD system. We describe the design and technical details of an apparatus which allows to attack a quantum-cryptographic connection. This device is capable of controlling free-space and fiber-based systems and of minimizing unwanted clicks in the system. With different control diagrams, we are able to achieve a different level of control. The control was initially targeted to the systems using BB84 protocol, with polarization encoding and basis switching using beamsplitters, but could be extended to other types of systems. We further outline how to characterize the quality of active control of single-photon detectors.Comment: 10 pages, 10 figure

A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter

The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. The achieved pixel pitch is 64μm with a fill factor of 3.5%. The chip was fabricated in a 0.18μm standard CMOS technology and implements a double functionality: Time-of-Flight estimation and photon counting. The imager features a programmable time resolution for the array of TDCs from 625ps down to 145ps. The measured accuracy of the minimum time bin is lower than ±1LSB DNL and 1.7LSB INL. The TDC jitter over the full dynamic range is less than 1LSB. Die-to-die process variation and temperature are discarded by auto-calibration. Fast quenching/restore circuit on each pixel lowers the power consumption by limiting the avalanche currents. Time gatedoperation is possible as well.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT- 2011-1625-430000, IPC- 20111009 CDTIJunta de Andalucía TIC 2012- 233