Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Perancangan produk jam dinding dengan material bonggol jagung

In general, the materials used in making wall clocks are metal, wood, and plastic. This research utilizes corn cobs as the main material for designing wall clock products that function as timepieces. With, through the design process of this research, a design by drawing approach was carried out which included the stages of analyzing existing industrial data, brainstorming to explore, define and conceptual criteria, as well as designing. Then, all three are formed into a sketch, and ends with making a product prototype. The purpose of this research is to be able to produce wall clock products made from corncobs as an innovation that can improve Indonesian industry, especially in the agro-industrial sector. The expected design result is that the role of this corncob-based wall clock can not only function as a timepiece. However, it can be one of the interior elements that builds good visual quality which in turn can support the atmosphere of the room and provide a novelty value by using corncob material in wall clock products

Timed Runtime Monitoring for Multiparty Conversations

We propose a dynamic verification framework for protocols in real-time distributed systems. The framework is based on Scribble, a tool-chain for design and verification of choreographies based on multiparty session types, developed with our industrial partners. Drawing from recent work on multiparty session types for real-time interactions, we extend Scribble with clocks, resets, and clock predicates constraining the times in which interactions should occur. We present a timed API for Python to program distributed implementations of Scribble specifications. A dynamic verification framework ensures the safe execution of applications written with our timed API: we have implemented dedicated runtime monitors that check that each interaction occurs at a correct timing with respect to the corresponding Scribble specification. The performance of our implementation and its practicability are analysed via benchmarking

A novel scan segmentation design method for avoiding shift timing failure in scan testing

ITC : 2011 IEEE International Test Conference , 20-22 Sep. 2011 , Anaheim, CA, USAHigh power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme

Efficient abstraction of clock synchronization at the operating system level

Distributed embedded systems are emerging and gaining importance in various domains, including industrial control applications where time determinism – hence network clock synchronization – is fundamental. In modern applications, moreover, this core functionality is required by many different software components, from OS kernel and radio stack up to applications. An abstraction layer devoted to handling time needs therefore introducing, and to encapsulate time corrections at the lowest possible level, the said layer should take the form of a timer device driver offering a Virtual Clock to the entire system. In this paper we show that doing so introduces a nonlinearity in the dynamics of the clock, and we design a controller based on feedback linearization to handle the issue. To put the idea to work, we extend the Miosix RTOS with a generic interface allowing to implement virtual clocks, including the newly designed controller that we call FLOPSYNC-3 after its ancestor. Also, we introduce the resulting virtual clock in the TDMH [20] real-time wireless mesh protocol

Lightweight Synchronization Algorithm with Self-Calibration for Industrial LORA Sensor Networks

Wireless sensor and actuator networks are gaining momentum in the era of Industrial Internet of Things IIoT. The usage of the close-loop data from sensors in the manufacturing chain is extending the common monitoring scenario of the Wireless Sensors Networks WSN where data were just logged. In this paper we present an accurate timing synchronization for TDMA implemented on the state of art IoT radio, such as LoRa, that is a good solution in industrial environments for its high robustness. Experimental results show how it is possible to modulate the drift correction and keep the synchronization error within the requirements

Analysis of the effect of clock drifts on frequency regulation and power sharing in inverter-based islanded microgrids

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Local hardware clocks in physically distributed computation devices hardly ever agree because clocks drift apart and the drift can be different for each device. This paper analyses the effect that local clock drifts have in the parallel operation of voltage source inverters (VSIs) in islanded microgrids (MG). The state-of-the-art control policies for frequency regulation and active power sharing in VSIs-based MGs are reviewed and selected prototype policies are then re-formulated in terms of clock drifts. Next, steady-state properties for these policies are analyzed. For each of the policies, analytical expressions are developed to provide an exact quantification of the impact that drifts have on frequency and active power equilibrium points. In addition, a closed-loop model that accommodates all the policies is derived, and the stability of the equilibrium points is characterized in terms of the clock drifts. Finally, the implementation of the analyzed policies in a laboratory MG provides experimental results that confirm the theoretical analysis.Peer ReviewedPostprint (author's final draft