Improvement of data refresh rate for dual serial port to universal serial bus acquisition system

Before the Universal Serial Bus (USB) Technologies has become popular, there are a lot of software and hardware computer peripheral development based on traditional external interface like General Purpose Interface Bus (GPIB- IEEE488), parallel port, serial port and PS/2. Developing these custom software and hardware computer peripheral is less difficult as compared to peripheral that is designed based on USB. The main reason for the difficulty is that the USB is designed to be user friendly but not developer friendly. For that reason, many developers will maintain using the traditional port when designing their custom application. To support traditional interface on newer PC with only USB port, there are devices in the market to convert the old external port to USB. One of the converters is the USB to dual serial converter. In the market, there are products which are readily available. However, it lacks of certain capability such as the ability to access serial port simultaneously which reduce the data refresh rate. The main purpose of this paper is to discuss technique in designing a USB to serial converter with capability of connecting two serial devices which is accessible simultaneously to improve the data refresh rate

An Interactive Training Device Using a Laser Video Disc

The goal of this paper is to develop an interactive training system. Although the system developed was used to train tank gunners, the system concepts are generic in that they can be applied to many training scenarios. Applications of computer-based training systems are briefly discussed. The system concepts are defined and hardware and software subsystems are outlined. An architectural overview will precede a detailed discussion of subsystems

Closed composting system controlled by PIC

This project analyses the different composting techniques existing nowadays and proposes a variant. This variant is going to be proved in a prototype. Humidity and temperature will be the sensed and controlled variables. Depending on the value of these parameters, the prototype will actuate to adjust them to the user‟s guides. This project gives a guide of the optimal temperature and humidity values of the whole process, but the prototype has been designed to permit variations of the process, so this is not only a prototype for the values gives, but a prototype for new experiments and new values First of all, the state of art and the composting process will be analyzed. Composting is a biological natural process that transforms organic waste to natural fertilizer. This process can be improved to get better material in less time. This deals us to the most important part: the control of the material to maintain it in the most proper condition. This report is divided in several parts: first of all, an introduction to the composting process and the state of art; then, the prototype will be explained; then all the hardware used for this project will be described; then there is a special mention to the PIC software and the PC software the prototype uses. At last the results of the tests performed and the conclusions and future ways of developing are shown

Integrated PV Performance Monitoring System

The main aim of this research work is to design an accurate and reliable monitoring system to be integrated with solar electricity generating system. The amount of solar energy received on the surface of the earth varies due to meteorological conditions and apparent trajectory of the sun. Due to this, the availability of sunlight is an average of 5-6 hours per day throughout the year in Malaysia. The performance monitoring system is required to ensure that the PV based solar electricity generating system is operating at an optimum level. The PV monitoring system is able to measure all the important parameters that determine an optimum performance. The measured values are recorded continuously, as the data acquisition system is connected to a computer, and data is stored at fixed intervals. The hardware is fully supported by software designed to give full flexibility in terms of data retrieval and processing. The data can be locally used and can be transmitted via internet for monitoring purposes. The data that appears directly on the local monitoring system is displayed via graphical user interface that was created by using Visualbasic.net. The Apache software was used to retrieve data from the internet. The transmitted data received by the remote terminal can be viewed by using any internet browser

Performance of thermoelectric cooling system with smart graphical user interface for solidifying liquid sample

A Thermoelectric Heat Pump (THP) controller system with smart Graphical User Interface (GUI) was introduced to solidify liquid samples for laser induced breakdown spectroscopy (LIBS) analysis. This paper describes the smart GUI and THP controller system based on the Arduino platform. The THP controller system was built to provide a user-friendly smart GUI for controlling the Peltier Thermoelectric Cooler (TEC) temperature and monitoring the sample temperature acquired from the temperature sensor. Instructions on the construction of the smart GUI and THP controller circuit were explained in this paper. The experimental results on solidifying distilled water and maintaining its freezing phase are presented in this work that demonstrated the excellent performance of the developed system

Electronic interface board to monitor and control CERN´s sputter ion pump

This report presents the work developed during the master internship at the European Organization for Nuclear Research (CERN). The described work resulted from two initial objectives: improvement of the control system of vacuum sectors and the development of a new Pro bus-DP intelligent slave interface board for sputter ion pump controllers. Since the objectives were distinct, the work was split into two di erent projects. In the rst project, the control system for vacuum sectors of Large Hadron Collider, Super Proton Synchrotron and Complex Proton Synchrotron was improved. A new control rmware based in VHDL was developed, tested and upgraded for the control cards. The second project presented in this report involved the development of an electronic card for sputter ion pump controllers. Currently, the communication between the Pro bus network and the ion pump controllers is performed by a remote input-output station based on the ET200 module from Siemens. The operation and status information of the ion pumps and their controllers provided to the network are limited since the remote input-output station does not acquire all the available signals. Moreover, the physical connections between the remote input-output station and each ion pump controller is done with a dedicated cable, which is prone to connection malfunctions. In order to reduce the complexity, improve the signal integrity and upgrade the monitoring and control of the ion pumps system, a new Pro bus-DP intelligent slave interface was developed. It aims to provide direct Pro bus connection to the ion pump controller and to give to the Pro bus master access to all its control signals, improving the controllers usability and exibility. In this report, the card topology, its internal modules, the rmware, the LabVIEW application and assessment tests are presented and described

Design Techniques for Energy-Quality Scalable Digital Systems

Energy efficiency is one of the key design goals in modern computing. Increasingly complex tasks are being executed in mobile devices and Internet of Things end-nodes, which are expected to operate for long time intervals, in the orders of months or years, with the limited energy budgets provided by small form-factor batteries. Fortunately, many of such tasks are error resilient, meaning that they can toler- ate some relaxation in the accuracy, precision or reliability of internal operations, without a significant impact on the overall output quality. The error resilience of an application may derive from a number of factors. The processing of analog sensor inputs measuring quantities from the physical world may not always require maximum precision, as the amount of information that can be extracted is limited by the presence of external noise. Outputs destined for human consumption may also contain small or occasional errors, thanks to the limited capabilities of our vision and hearing systems. Finally, some computational patterns commonly found in domains such as statistics, machine learning and operational research, naturally tend to reduce or eliminate errors. Energy-Quality (EQ) scalable digital systems systematically trade off the quality of computations with energy efficiency, by relaxing the precision, the accuracy, or the reliability of internal software and hardware components in exchange for energy reductions. This design paradigm is believed to offer one of the most promising solutions to the impelling need for low-energy computing. Despite these high expectations, the current state-of-the-art in EQ scalable design suffers from important shortcomings. First, the great majority of techniques proposed in literature focus only on processing hardware and software components. Nonetheless, for many real devices, processing contributes only to a small portion of the total energy consumption, which is dominated by other components (e.g. I/O, memory or data transfers). Second, in order to fulfill its promises and become diffused in commercial devices, EQ scalable design needs to achieve industrial level maturity. This involves moving from purely academic research based on high-level models and theoretical assumptions to engineered flows compatible with existing industry standards. Third, the time-varying nature of error tolerance, both among different applications and within a single task, should become more central in the proposed design methods. This involves designing “dynamic” systems in which the precision or reliability of operations (and consequently their energy consumption) can be dynamically tuned at runtime, rather than “static” solutions, in which the output quality is fixed at design-time. This thesis introduces several new EQ scalable design techniques for digital systems that take the previous observations into account. Besides processing, the proposed methods apply the principles of EQ scalable design also to interconnects and peripherals, which are often relevant contributors to the total energy in sensor nodes and mobile systems respectively. Regardless of the target component, the presented techniques pay special attention to the accurate evaluation of benefits and overheads deriving from EQ scalability, using industrial-level models, and on the integration with existing standard tools and protocols. Moreover, all the works presented in this thesis allow the dynamic reconfiguration of output quality and energy consumption. More specifically, the contribution of this thesis is divided in three parts. In a first body of work, the design of EQ scalable modules for processing hardware data paths is considered. Three design flows are presented, targeting different technologies and exploiting different ways to achieve EQ scalability, i.e. timing-induced errors and precision reduction. These works are inspired by previous approaches from the literature, namely Reduced-Precision Redundancy and Dynamic Accuracy Scaling, which are re-thought to make them compatible with standard Electronic Design Automation (EDA) tools and flows, providing solutions to overcome their main limitations. The second part of the thesis investigates the application of EQ scalable design to serial interconnects, which are the de facto standard for data exchanges between processing hardware and sensors. In this context, two novel bus encodings are proposed, called Approximate Differential Encoding and Serial-T0, that exploit the statistical characteristics of data produced by sensors to reduce the energy consumption on the bus at the cost of controlled data approximations. The two techniques achieve different results for data of different origins, but share the common features of allowing runtime reconfiguration of the allowed error and being compatible with standard serial bus protocols. Finally, the last part of the manuscript is devoted to the application of EQ scalable design principles to displays, which are often among the most energy- hungry components in mobile systems. The two proposals in this context leverage the emissive nature of Organic Light-Emitting Diode (OLED) displays to save energy by altering the displayed image, thus inducing an output quality reduction that depends on the amount of such alteration. The first technique implements an image-adaptive form of brightness scaling, whose outputs are optimized in terms of balance between power consumption and similarity with the input. The second approach achieves concurrent power reduction and image enhancement, by means of an adaptive polynomial transformation. Both solutions focus on minimizing the overheads associated with a real-time implementation of the transformations in software or hardware, so that these do not offset the savings in the display. For each of these three topics, results show that the aforementioned goal of building EQ scalable systems compatible with existing best practices and mature for being integrated in commercial devices can be effectively achieved. Moreover, they also show that very simple and similar principles can be applied to design EQ scalable versions of different system components (processing, peripherals and I/O), and to equip these components with knobs for the runtime reconfiguration of the energy versus quality tradeoff

Developing a Wireless Sensor Network Programming Language Application Guide Using Memsic Devices and LabVIEW

The principal objective of this project is to develop a wireless sensor network (WSN) programming language application guide for junior and senior undergraduate students in College of Technology, Architecture and Applied Engineering in Bowling Green State University. Memsic device, MoteWorks and LabVIEW software are used to conduct experiments in developing WSN applications after both software and hardware platform are verified to be usable with experimental and statistical analysis. The guide is divided into six chapters including both theoretical knowledge and practical experiments in WSN area. Programs, both in nesC language and LabVIEW are improved from previous work, tested to run successfully and noted in detail

FPGA embedded system for ultrasonic non-destructive testing

This thesis was submitted for the award of Doctor of Philosophy and was awarded by Brunel University LondonLong Range Ultrasonic Testing (LRUT) is an emerging ultrasound Non-destructive Testing (NDT) method. The LRUT is a variant of the conventional NDT approach. By using ultrasound guided waves (UGWs) , it is efficient in quick long range defect scanning, which is impossible with other traditional NDT techniques. Increasing numbers of requirements for quick long range testing have led to urgent need for the improvement of testing methods and the development of new testing equipment to help researchers in laboratory and help technicians in field inspection. The market for multi-channel ultrasonic instruments is characterized by small volumes of sales and a high ratio of development costs to sale price. The consequence is that the investment required to develop an instrument is significant and upgrades and other changes to instrument specification or configuration are difficult for many manufacturers to justify. These factors are particularly relevant for long range guided wave technology, where the technology is still relatively new in the market place and the instrumentation has different characteristics from other type of ultrasonic systems. In order to support the design and manufacture of the Teletest®MK4 system, Plant Integrity Ltd has supported this study into the use of a field-programmable gates array (FPGA) based control circuits for the electronics, which allows the component count to be decreased and also permits the system to be modified via flexible reconfiguration of the FPGA. This has benefits of reduction of size, weight and power consumption of the electronics and provides a means of upgrading the product without expensive re-design of the hardware. FPGA device has been the enabling technology and main thrust behind the evolution of many technologies, unleashing new opportunities for improving the performance of the LRUT equipment and providing more functions for industrial and academic applications. A novel system has been developed to provide multichannel waveform generation, data capture and signal processing for advanced lab-based research and faster- field testing. This system includes an FPGA to process multichannel data in parallel and to provide the flexibility of reconfiguration for various testing applications proposed by new research. The design was tested in pre-prototype hardware. Subsequent construction of the commercial prototype unit enabled successful operation of the design to be demonstrated. Implementation of the FPGA design reduced component count, PCB dimensions and power consumption. Though the SpartanTM 3A DSP FPGA and Xilinx ISE software have been used in this project, the concepts of the design can be applied to other FPGA devices from other FPGA vendors using other design softwares.TWI Ltd; Plant Integrity Lt

An SOPC Based Image Processing System

Recent advances in semiconductor technology have made it possible to integrate an entire system including processors, memory and other system units into a single programmable chip - FPGA, these configurations are called 'System-on-aProgrammable- Chip' (SOPC). SOPCs have the advantage that they can be designed quicker than existing technologies and are cheap to produce for low volume «10,000) applications. Also, SOPCs are of great benefit as they offer compact and flexible system designs due to their reconfigurable nature and high integration of features. One processor intensive application, which is ideal for SOPC technology, is that of image processing where there is a repeated application of operations on the 2D data. This research investigated the use of SOPC technology for image processing by developing a modular system capable ofreal-time video acquisition, processing and display. An sope Based Image Processing System Abstract Abstract This system is comprised of a CameraLink CMOS camera with a custom designed camera interface card for video acquisition, a VGA mode CRT monitor with a Lancelot VGA card for video display, an industrial SDRAM device for video data buffering, and an Altera Apex 20K FPGA for evaluating the SOPC design. Four custom designed IP components have been developed and integrated with other Altera provided standard IP components to drive all off-chip peripherals and perform the required video functions such as processing the images. These custom designed IPs are the video capture controller, video display controller, video memory controller and Cache. A Nios processor was chosen to perform the actual image processing, and the whole system was developed on the Altera Nios development board. In order to solve the complex on-chip data communication, while not degrading the transferring speed of largeamounts of video data, an effective solution called Simultaneously Multi-Mastering Avalon Streaming Transfer with Peripheral-Controlled Waitrequest was raised. Rather than using the software approach to initialise DMA-like transfers, this solution takes advantage of the FPGA hardware resource to perform bus arbitration and hence increases the system efficiency. The system produced is an alternative to conventional desktop-based, i.e. a visionbased closed loop process control system for weiding, or microprocessor-based vision systems. September 2007 FanWu Supplied by The British Library - 'The world's knowledge