Digital Pulse Width Modulator Techniques For Dc - Dc Converters

Recent research activities focused on improving the steady-state as well as the dynamic behavior of DC-DC converters for proper system performance, by proposing different design methods and control approaches with growing tendency to using digital implementation over analog practices. Because of the rapid advancement in semiconductors and microprocessor industry, digital control grew in popularity among PWM converters and is taking over analog techniques due to availability of fast speed microprocessors, flexibility and immunity to noise and environmental variations. Furthermore, increased interest in Field Programmable Gate Arrays (FPGA) makes it a convenient design platform for digitally controlled converters. The objective of this research is to propose new digital control schemes, aiming to improve the steady-state and transient responses of a high switching frequency FPGA-based digitally controlled DC-DC converters. The target is to achieve enhanced performance in terms of tight regulation with minimum power consumption and high efficiency at steady-state, as well as shorter settling time with optimal over- and undershoots during transients. The main task is to develop new and innovative digital PWM techniques in order to achieve: 1. Tight regulation at steady-state: by proposing high resolution DPWM architecture, based on Digital Clock Management (DCM) resources available on FPGA boards. The proposed architecture Window-Masked Segmented Digital Clock Manager-FPGA based Digital Pulse Width Modulator Technique, is designed to achieve high resolution operating at high switching frequencies with minimum power consumption. 2. Enhanced dynamic response: by applying a shift to the basic saw-tooth DPWM signal, in order to benefit from the best linearity and simplest architecture offered by the conventional counter-comparator DPWM. This proposed control scheme will help the compensator reach the steady-state value faster. Dynamically Shifted Ramp Digital Control Technique for Improved Transient Response in DC-DC Converters, is projected to enhance the transient response by dynamically controlling the ramp signal of the DPWM unit

A peak capacitor current pulse-train controlled buck converter with fast transient response and a wide load range

It is known that ripple-based control of a switching dc-dc converter benefits from a faster transient response than a conventional PWM control switching dc-dc converter. However, ripple-based control switching dc-dc converters may suffer from fast-scale oscillation. In order to achieve fast transient response and ensure stable operation of a switching dc-dc converter over a wide load range, based on a conventional pulse train control technique, a peak capacitor current pulse train (PCC-PT) control technique is proposed in this paper. With a buck converter as an example, the operating modes, steady-state performance and transient respond performance of a PCC-PT controlled buck converter are presented and assessed. To eliminate fast-scale oscillation, circuit and control parameter design consideration are given. An accurate discrete iteration model of a PCC-PT controlled buck converter is established, based on which, the effects of circuit parameters on stability of converter operating in a DCM mode, mixed DCM-CCM mode, and CCM mode are studied. Simulation and experimental results are presented to verify the analysis results

Low Voltage Regulator Modules and Single Stage Front-end Converters

Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding 1GHz. New high-performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response. In the part one (chapter 2,3,4) of this dissertation, several low-voltage high-current VRM technologies are proposed for future generation microprocessors and ICs. The developed VRMs with these new technologies have advantages over conventional ones in terms of efficiency, transient response and cost. In most cases, the VRMs draw currents from DC bus for which front-end converters are used as a DC source. As the use of AC/DC frond-end converters continues to increase, more distorted mains current is drawn from the line, resulting in lower power factor and high total harmonic distortion. As a branch of active Power factor correction (PFC) techniques, the single-stage technique receives particular attention because of its low cost implementation. Moreover, with continuously demands for even higher power density, switching mode power supply operating at high-frequency is required because at high switching frequency, the size and weight of circuit components can be remarkably reduced. To boost the switching frequency, the soft-switching technique was introduced to alleviate the switching losses. The part two (chapter 5,6) of the dissertation presents several topologies for this front-end application. The design considerations, simulation results and experimental verification are discussed

A Control Scheme for an AC-DC Single-Stage Buck-Boost PFC Converter with Improved Output Ripple Reduction

AC-DC power factor correction (PFC) single-stage converters are attractive because of their cost and their simplicity. In these converters, both PFC and power conversion are done at the same time using a single converter that regulates the output. Since they have only a single controller, these converters operate with an intermediate transformer primary-side DC bus voltage that is unregulated and is dependent on the converters’ operating conditions and component values. This means that the DC bus voltage can vary significantly as line and load conditions are changed. Such a variable DC bus voltage makes it difficult to optimally design the converter transformer as well as the DC bus capacitor. One previously proposed single-stage AC-DC converter, the Single-Stage Buck-Boost Direct Energy Transfer (SSBBDET) converter has a clamping mechanism that can clamp the DC bus voltage to a pre-set limit. The clamping mechanism, however, superimposes a low frequency 120 Hz AC component on the output DC voltage so that some means must be taken to reduce this component. These means, however, make the converter transient slow and sluggish. The main objective of this thesis is to minimize the 120 Hz output ripple component and to improve the dynamic response of the SSBBDET converter by using a new control scheme. In the thesis, the operation of the SSBBDET converter is reviewed and the proposed control method is introduced and explained in detail. Key design considerations for the design of the converter controller are discussed and the converter’s ability to operate with fixed DC bus voltage, low output ripple and fast dynamic response is confirmed with experimental results obtained from a prototype converter

Adaptive Efficiency Optimization For Digitally Controlled Dc-dc Converters

The design optimization of DC-DC converters requires the optimum selection of several parameters to achieve improved efficiency and performance. Some of these parameters are load dependent, line dependent, components dependent, and/or temperature dependent. Designing such parameters for a specific load, input and output, components, and temperature may improve single design point efficiency but will not result in maximum efficiency at different conditions, and will not guarantee improvement at that design point because of the components, temperature, and operating point variations. The ability of digital controllers to perform sophisticated algorithms makes it easy to apply adaptive control, where system parameters can be adaptively adjusted in response to system behavior in order to achieve better performance and stability. The use of adaptive control for power electronics is first applied with the Adaptive Frequency Optimization (AFO) method, which presents an auto-tuning adaptive digital controller with maximum efficiency point tracking to optimize DC-DC converter switching frequency. The AFO controller adjusts the DC-DC converter switching frequency while tracking the converter minimum input power point, under variable operating conditions, to find the optimum switching frequency that will result in minimum total loss and thus the maximum efficiency. Implementing variable switching frequencies in digital controllers introduces two main issues, namely, limit cycle oscillation and system instability. Dynamic Limit Cycle Algorithms (DLCA) is a dynamic technique tailored to improve system stability and to reduce limit cycle oscillation under variable switching frequency operation. The convergence speed and stability of AFO algorithm is further improved by presenting the analysis and design of a digital controller with adaptive auto-tuning algorithm that has a variable step size to track and detect the optimum switching frequency for a DC-DC converter. The Variable-Step-Size (VSS) algorithm is theoretically analyzed and developed based on buck DC-DC converter loss model and directed towered improving the convergence speed and accuracy of AFO adaptive loop by adjusting the converter switching frequency with variable step size. Finally, the efficiency of DC-DC converters is a function of several variables. Optimizing single variable alone may not result in maximum or global efficiency point. The issue of adjusting more than one variable at the same time is addressed by the Multivariable Adaptive digital Controller (MVAC). The MVAC is an adaptive method that continuously adjusts the DC-DC converter switching frequency and dead-time at the same time, while tracking the converter minimum input power, to find the maximum global efficiency point under variable conditions. In this research work, all adaptive methods were discussed, theoretically analyzed and its digital control algorithm along with experimental implementations were presented

Multi-harmonic Modeling of Low-power PWM DC-DC Converter

Modeling and simulation of switched-mode Pulse Width Modulated (PWM) DC-DC converters form an essential ingredient in the analysis and design process of integrated circuits. In this research work, we present a novel large-signal modeling technique for low-power PWM DC-DC converters. The proposed model captures not only the time-averaged response within each moving switching cycle but also high-order harmonics of an arbitrary degree, hence modeling both the average component and ripple very accurately. The proposed model retains the inductor current as a state variable and accurately captures the circuit dynamics even in the transient state. By continuously monitoring state variables, our model seamlessly transitions between the continuous conduction mode (CCM) and discontinuous conduction mode (DCM), which often occurs in low-power applications. The nonlinearities of devices are also considered and efficiently evaluated resulting in a significant improvement in model accuracy. With a system decoupling technique, the DC response of the model is decoupled from higher-order harmonics, providing additional simulation speedups. For a number of converter designs, the proposed model obtains up to 10x runtime speedups over transistor-level transient simulation with a maximum output voltage error less than 4%

The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

Dynamic modeling of pwm and single-switch single-stage power factor correction converters

The concept of averaging has been used extensively in the modeling of power electronic circuits to overcome their inherent time-variant nature. Among various methods, the PWM switch modeling approach is most widely accepted in the study of closed-loop stability and transient response because of its accuracy and simplicity. However, a non-ideal PWM switch model considering conduction losses is not available except for converters operating in continuous conduction mode (CCM) and under small ripple conditions. Modeling of conductor losses under large ripple conditions has not been reported in the open literature, especially when the converter operates in discontinuous conduction mode (DCM). In this dissertation, new models are developed to include conduction losses in the non-ideal PWM switch model under CCM and DCM conditions. The developed model is verified through two converter examples and the effect of conduction losses on the steady state and dynamic responses of the converter is also studied. Another major constraint of the PWM switch modeling approach is that it heavily relies on finding the three-terminal PWM switch. This requirement severely limits its application in modeling single-switch single-stage power factor correction (PFC) converters, where more complex topological structures and switching actions are often encountered. In this work, we developed a new modeling approach which extends the PWM switch concept by identifying the charging and discharging voltages applied to the inductors. The new method can be easily applied to derive large-signal models for a large group of PFC converters and the procedure is elaborated through a specific example. Finally, analytical results regarding harmonic contents and power factors of various PWM converters in PFC applications are also presented here