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Spin-Based Neuron Model with Domain Wall Magnets as Synapse

We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed

Modeling of Total Ionizing Dose Effects in Advanced Complementary Metal-Oxide-Semiconductor Technologies

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.Dissertation/ThesisPh.D. Electrical Engineering 201

NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE

Experiment has proven that NMOS performs better than PMOS due to higher drive current, higher mobility, easier to implement scaling technology and low power consumption. However, there is still room for further optimization as the technology trend for the miniaturization ofNMOS and integrated devices continue to grow. In this project, several objectives have been outlined to be completed within 2 semester period. These include detailed understanding of fabrication aspect and NMOS properties, optimizing NMOS by reducing threshold voltage, minimizing off-stage leakage, reducing gate length, increasing switching speed and designing a mixed mode circuit. However, the cost required to perform experimental analysis and optimization of semiconductor devices using fabrication process can be very expensive especially when involving purchase of expensive electrical testing equipment. Thus, it is recommended to perform optimization and analysis using simulation. One ofthe best device process and simulation tool is Silvaco ATHENA & ATLAS simulation software. It provides user with various capability in process and electrical testing. After manipulating and improving process parameters, the optimized device has recorded significant improvement over the predecessor. Optimizations include better threshold voltage extraction (0.2v), drain current rise beyond pinch off, better drain current extraction, higher switching speed at 2Ghz, better device structure after ion implantation due to tilted implantation, lower off-stage leakage current (1.2589 x 10' A/um) and minimization ofjunction breakdown effect

Monte Carlo simulation of silicon-germanium transistors

Self-consistent Monte Carlo simulation studies of n-channel Si/SiGe modulation doped field effect transistors (MODFETs) and silicon-on-insulator lateral bipolar junction transistors (SOI- LBJTs) are reported in this thesis. As a preliminary to the device studies Monte Carlo simulations of electron transport in bulk Si strained as if grown on Si(_0.77)Ge(_0.23) and Si(_0.55)Ge(_0.45) substrates have been carried out at 300 K, for field strengths varied from 10(^4) to 2 x 10(^7) Vm(^-1). The calculations indicate an enhancement of the average electron drift velocity when Si is tensilely strained in the growth plane. The enhancement of electron velocity is more marked at low and intermediate electric fields, while at very high fields the velocity saturates at about the same value as unstrained Si. In addition the ensemble Monte Carlo method has been used to study the transient response to a stepped electric field of electrons in strained and unstrained Si. The calculations suggest that significant velocity overshoots occurs in strained material. Simulations of n-channel Si/Si(_1=z)Ge(_z) MODFETs with Ge fractions of 0.23, 0.25, and 0.45 have been performed. Five depletion mode devices with x = 0.23 and 0.25 were studied. The simulations provide information on the microscopic details of carrier behaviour, including carrier velocity, kinetic energy and carrier density, as a function of position in the device. Detailed time-dependent voltage signal analysis has been carried out to test device response and derive the frequency bandwidth. The simulations predict a current gain cut-off frequency of 60 ± 10 GHz for a device with a gate length of 0.07 /nm and a channel length of 0.25 um. Similar studies of depletion and enhancement mode n-channel Si/Sio.55Geo.45 MODFETs with a gate length of 0.18 /im have been carried out. Cut-off frequencies of 60 ±10 GHz and 90± 10 GHz are predicted for the depletion and enhancement mode devices respectively. A Monte Carlo model has also been devised and used to simulate steady state and transient electron and hole transport in SOI-LBJTs. Four devices have been studied and the effects of junction depth and silicon layer thickness have been investigated. The advantage of the silicon-on-insulator technology SOI device is apparent in terms of higher collector current, current gain, and cut-off frequency obtained in comparison with an all-silicon structure. The simulations suggest that the common-emitter current gain of the most promising SOI-LBJT structure considered could have a cut-off frequency approaching 35 ± 5 GHz

Non-linear thermal resistance model for the simulation of high power GaN-based devices

[EN]We report on the modeling of self-heating in GaN-based devices. While a constant thermal resistance is able to account for the self-heating effects at low power, the decrease of the thermal conductance of semiconductors when the lattice temperature increases, makes necessary the use of temperature dependent thermal resistance models. Moreover, in order to correctly account for the steep increase of the thermal resistance of GaN devices at high temperature, where commonly used models fail, we propose a non-linear model which, included in an electro-thermal Monte Carlo simulator, is able to reproduce the strongly non-linear behavior of the thermal resistance observed in experiments at high DC power levels. The accuracy of the proposed non-linear thermal resistance model has been confirmed by means of the comparison with pulsed and DC measurements made in devices specifically fabricated on doped GaN, able to reach DC power levels above 150 W mm−1 at biases below 30 V.NRF2017-NRFANR003 GaNGUN project, the Spanish MINECO and FEDER through project TEC2017-83910-R and the Junta de Castilla y León and FEDER through project SA254P18