Retracting Graphs to Cycles

We initiate the algorithmic study of retracting a graph into a cycle in the graph, which seeks a mapping of the graph vertices to the cycle vertices so as to minimize the maximum stretch of any edge, subject to the constraint that the restriction of the mapping to the cycle is the identity map. This problem has its roots in the rich theory of retraction of topological spaces, and has strong ties to well-studied metric embedding problems such as minimum bandwidth and 0-extension. Our first result is an O(min{k, sqrt{n}})-approximation for retracting any graph on n nodes to a cycle with k nodes. We also show a surprising connection to Sperner\u27s Lemma that rules out the possibility of improving this result using certain natural convex relaxations of the problem. Nevertheless, if the problem is restricted to planar graphs, we show that we can overcome these integrality gaps by giving an optimal combinatorial algorithm, which is the technical centerpiece of the paper. Building on our planar graph algorithm, we also obtain a constant-factor approximation algorithm for retraction of points in the Euclidean plane to a uniform cycle

The hardness of perfect phylogeny, feasible register assignment and other problems on thin colored graphs

AbstractIn this paper, we consider the complexity of a number of combinatorial problems; namely, Intervalizing Colored Graphs (DNA physical mapping), Triangulating Colored Graphs (perfect phylogeny), (Directed) (Modified) Colored Cutwidth, Feasible Register Assignment and Module Allocation for graphs of bounded pathwidth. Each of these problems has as a characteristic a uniform upper bound on the tree or path width of the graphs in “yes”-instances. For all of these problems with the exceptions of Feasible Register Assignment and Module Allocation, a vertex or edge coloring is given as part of the input. Our main results are that the parameterized variant of each of the considered problems is hard for the complexity classes W[t] for all t∈N. We also show that Intervalizing Colored Graphs, Triangulating Colored Graphs, and Colored Cutwidth are NP-Complete

BDD-based heuristics for binary optimization

In this paper we introduce a new method for generating heuristic solutions to binary optimization problems. We develop a technique based on binary decision diagrams. We use these structures to provide an under-approximation to the set of feasible solutions. We show that the proposed algorithm delivers comparable solutions to a state-of-the-art general-purpose optimization solver on randomly generated set covering and set packing problems

Parameterized complexity of Bandwidth of Caterpillars and Weighted Path Emulation

In this paper, we show that Bandwidth is hard for the complexity class $W[t]$ for all $t\in {\bf N}$, even for caterpillars with hair length at most three. As intermediate problem, we introduce the Weighted Path Emulation problem: given a vertex-weighted path $P_N$ and integer $M$, decide if there exists a mapping of the vertices of $P_N$ to a path $P_M$, such that adjacent vertices are mapped to adjacent or equal vertices, and such that the total weight of the image of a vertex from $P_M$ equals an integer $c$. We show that {\sc Weighted Path Emulation}, with $c$ as parameter, is hard for $W[t]$ for all $t\in {\bf N}$, and is strongly NP-complete. We also show that Directed Bandwidth is hard for $W[t]$ for all $t\in {\bf N}$, for directed acyclic graphs whose underlying undirected graph is a caterpillar.Comment: 31 pages; 9 figure

Automating Topology Aware Mapping for Supercomputers

Petascale machines with hundreds of thousands of cores are being built. These machines have varying interconnect topologies and large network diameters. Computation is cheap and communication on the network is becoming the bottleneck for scaling of parallel applications. Network contention, specifically, is becoming an increasingly important factor affecting overall performance. The broad goal of this dissertation is performance optimization of parallel applications through reduction of network contention. Most parallel applications have a certain communication topology. Mapping of tasks in a parallel application based on their communication graph, to the physical processors on a machine can potentially lead to performance improvements. Mapping of the communication graph for an application on to the interconnect topology of a machine while trying to localize communication is the research problem under consideration. The farther different messages travel on the network, greater is the chance of resource sharing between messages. This can create contention on the network for networks commonly used today. Evaluative studies in this dissertation show that on IBM Blue Gene and Cray XT machines, message latencies can be severely affected under contention. Realizing this fact, application developers have started paying attention to the mapping of tasks to physical processors to minimize contention. Placement of communicating tasks on nearby physical processors can minimize the distance traveled by messages and reduce the chances of contention. Performance improvements through topology aware placement for applications such as NAMD and OpenAtom are used to motivate this work. Building on these ideas, the dissertation proposes algorithms and techniques for automatic mapping of parallel applications to relieve the application developers of this burden. The effect of contention on message latencies is studied in depth to guide the design of mapping algorithms. The hop-bytes metric is proposed for the evaluation of mapping algorithms as a better metric than the previously used maximum dilation metric. The main focus of this dissertation is on developing topology aware mapping algorithms for parallel applications with regular and irregular communication patterns. The automatic mapping framework is a suite of such algorithms with capabilities to choose the best mapping for a problem with a given communication graph. The dissertation also briefly discusses completely distributed mapping techniques which will be imperative for machines of the future.published or submitted for publicationnot peer reviewe

Energy-aware synthesis for networks on chip architectures

The Network on Chip (NoC) paradigm was introduced as a scalable communication infrastructure for future System-on-Chip applications. Designing application specific customized communication architectures is critical for obtaining low power, high performance solutions. Two significant design automation problems are the creation of an optimized configuration, given application requirement the implementation of this on-chip network. Automating the design of on-chip networks requires models for estimating area and energy, algorithms to effectively explore the design space and network component libraries and tools to generate the hardware description. Chip architects are faced with managing a wide range of customization options for individual components, routers and topology. As energy is of paramount importance, the effectiveness of any custom NoC generation approach lies in the availability of good energy models to effectively explore the design space. This thesis describes a complete NoC synthesis flow, called NoCGEN, for creating energy-efficient custom NoC architectures. Three major automation problems are addressed: custom topology generation, energy modeling and generation. An iterative algorithm is proposed to generate application specific point-to-point and packet-switched networks. The algorithm explores the design space for efficient topologies using characterized models and a system-level floorplanner for evaluating placement and wire-energy. Prior to our contribution, building an energy model required careful analysis of transistor or gate implementations. To alleviate the burden, an automated linear regression-based methodology is proposed to rapidly extract energy models for many router designs. The resulting models are cycle accurate with low-complexity and found to be within 10% of gate-level energy simulations, and execute several orders of magnitude faster than gate-level simulations. A hardware description of the custom topology is generated using a parameterizable library and custom HDL generator. Fully reusable and scalable network components (switches, crossbars, arbiters, routing algorithms) are described using a template approach and are used to compose arbitrary topologies. A methodology for building and composing routers and topologies using a template engine is described. The entire flow is implemented as several demonstrable extensible tools with powerful visualization functionality. Several experiments are performed to demonstrate the design space exploration capabilities and compare it against a competing min-cut topology generation algorithm

Related Orderings of AT-Free Graphs

An ordering of a graph G is a bijection of V(G) to {1, . . . , |V(G)|}. In this thesis, we consider the complexity of two types of ordering problems. The first type of problem we consider aims at minimizing objective functions related to an ordering of the graph. We consider the problems Cutwidth, Imbalance, and Optimal Linear Arrangement. We also consider a problem of another type: S-End-Vertex, where S is one of the following search algorithms: breadth-first search (BFS), lexicographic breadth-first search (LBFS), depth-first search (DFS), and maximal neighbourhood search (MNS). This problem asks if a specified vertex can be the last vertex in an ordering generated by S. We show that, for each type of problem, orderings for one problem may be related to orderings for another problem of that type. We show that there is always a cutwidth-minimal ordering where equivalence classes of true twins are grouped for any graph, where true twins are vertices with the same closed neighbourhood. This enables a fixed-parameter tractable (FPT) algorithm for Cutwidth on graphs parameterized by the edge clique cover number of the graph and a new parameter, the restricted twin cover number of the graph. The restricted twin cover number of the graph generalizes the vertex cover number of a graph, and is the smallest value k ≥ 0 such that there is a twin cover of the graph T and k−|T| non-trivial components of G−T. We show that there is also always an imbalance-minimal ordering where equivalence classes of true twins are grouped for any graph. We show a polynomial time algorithm for this problem on superfragile graphs and subsets of proper interval graphs, both subsets of AT-free graphs. An asteroidal triple (AT) is a triple of independent vertices x, y, z such that between every pair of vertices in the triple, there is a path that does not intersect the closed neighbourhood of the third. A graph without an asteroidal triple is said to be AT-free. We also provide closed formulas for Imbalance on some small graph classes. In the FPT setting, we improve algorithms for Imbalance parameterized by the vertex cover number of the input graph and show that the problem does not have a polynomially sized kernel for the same parameter number unless NP ⊆ coNP/poly. We show that Optimal Linear Arrangement also has a polynomial algorithm for superfragile graphs and an FPT algorithm with respect to the restricted twin cover number. Finally, we consider S-End-Vertex, for BFS, LBFS, DFS, and MNS. We perform the first systematic study of the problem on bipartite permutation graphs, a subset of AT-free graphs. We show that for BFS and MNS, the problem has a polynomial time solution. We improve previous results for LBFS, obtaining a linear time algorithm. For DFS, we establish a linear time algorithm. All the results follow from the linear structure of bipartite permutation graphs

2D Phase Unwrapping via Graph Cuts

Phase imaging technologies such as interferometric synthetic aperture radar (InSAR), magnetic resonance imaging (MRI), or optical interferometry, are nowadays widespread and with an increasing usage. The so-called phase unwrapping, which consists in the in- ference of the absolute phase from the modulo-2π phase, is a critical step in many of their processing chains, yet still one of its most challenging problems. We introduce an en- ergy minimization based approach to 2D phase unwrapping. In this approach we address the problem by adopting a Bayesian point of view and a Markov random field (MRF) to model the phase. The maximum a posteriori estimation of the absolute phase gives rise to an integer optimization problem, for which we introduce a family of efficient algo- rithms based on existing graph cuts techniques. We term our approach and algorithms PUMA, for Phase Unwrapping MAx flow. As long as the prior potential of the MRF is convex, PUMA guarantees an exact global solution. In particular it solves exactly all the minimum L p norm (p ≥ 1) phase unwrapping problems, unifying in that sense, a set of existing independent algorithms. For non convex potentials we introduce a version of PUMA that, while yielding only approximate solutions, gives very useful phase unwrap- ping results. The main characteristic of the introduced solutions is the ability to blindly preserve discontinuities. Extending the previous versions of PUMA, we tackle denoising by exploiting a multi-precision idea, which allows us to use the same rationale both for phase unwrapping and denoising. Finally, the last presented version of PUMA uses a frequency diversity concept to unwrap phase images having large phase rates. A representative set of experiences illustrates the performance of PUMA

A computational framework for sound segregation in music signals

Tese de doutoramento. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200