Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology

Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core

The current implementation of dynamic voltage and frequency scaling (DVS and DFS) in microprocessors is based on a single clock domain per core. In architectures that adopt Instruction Level Parallelism (ILP), multiple execution units may exist and operate concurrently. Performing DVS and DFS on such cores may result in low utilization and power efficiency. In this thesis, a methodology that implements DVFS with multi Clock distribution Systems (DCS) is applied on a processor core to achieve higher throughput and better power efficiency. DCS replaces the core single clock distribution tree with multi-clock domain systems which, along with dynamic voltage and frequency scaling, creates multiple clock-voltage domains. DCS implements a self-timed interface between the different domains to maintain functionality and ensure data integrity. DCS was implemented on a SPARC core of UltraSPARC T1 architecture, and synthesized targeting TSMC 120nm process technology. Two clock domains were used on SPARC core. The maximum achieved speedup relative to original core was 1.6X. The power consumed by DCS was 0.173mW compared to the core total power of ~ 10W

Novel dual-Vth independent-gate FinFET circuits

This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.NSF CAREER Award CCF-074685

HPP : a high performance PRAM

We present a fast shared memory multiprocessor with uniform memory access time. A first prototype (SB-PRAM) is running with 4 processors, a 128 processor version is under construction. A second implementation (HPP) using latest VLSI technology and optical links shall run at a speed of 96 MHz. To achieve this speed, we first investigate the re-design of ASICs and network links. We then balance processor speed and memory bandwidth by investigating the relation between local computation and global memory access in several benchmark applications. On numerical codes such as linpack, 2 and 8 GFlop/s shall be possible with 128 and 512 processors, respectively, thus approaching processor performance of Intel Paragon XPS. As non-numerical codes we consider circuit simulation and raytracing. We achieve speedups over a one processor SGI challenge of 35 and 81 for 128 processors and 140 and 325 for 512 processors

Mechanism of damage to fibronectin by myeloperoxidase derived oxidants

Atherosclerosis is characterised by lipid deposition in the arterial wall and chronic low-grade inflammation. Leukocytes migrate to the area of injury and release the heme enzyme myeloperoxidase (MPO) into the extracellular matrix (ECM). This enzyme converts H2O2 to hypohalous acids (e.g.HOCl from Cl-, HOSCN from SCN-). There is considerable evidence that these oxidants, particularly HOCl, damage cells and the ECM, and contribute to cardiovascular disease. HOCl is a highly damaging oxidant, whereas HOSCN is less reactive and generates reversible modifications. The ECM contains multiple proteins, including fibronectin (FN), which are critical to matrix assembly and cell function. FN possesses multiple functionally-important epitopes including a cell binding fragment (CBF) and a heparin binding fragment (HBF). The co-localisation of FN and MPO in the ECM, makes FN a likely target for MPO-derived oxidants. Therefore, this project aimed to elucidate the effects of HOCl and HOSCN on FN, and whether the increasing SCN- concentrations modulated ECM damage induced by HOCl. Exposure of human plasma FN to HOCl resulted in fragmentation and aggregation of the protein, formation of modified amino acids, and alterations to the CBF and HBF. Human coronary artery endothelial cells exposed to modified FN showed poor adhesion, impaired cell spreading, reduced metabolic activity and altered gene expression. In contrast, reagent HOSCN generated limited modifications. Studies using an enzymatic MPO/H2O2 system with either Cl- or SCN-, showed that MPO/H2O2/Cl- gave extensive FN modifications, whereas MPO/H2O2/SCN- induced only minor changes. When both Cl- and SCN- were present as competing substrates, increasing concentrations of SCN- decreased the extent of chemical and structural modifications detected on FN supporting the hypothesis that increasing the concentration of SCN- may mitigate damage generated by the MPO/Cl-/H2O2 system and potentially modulate disease development

Energy-Aware Data Management on NUMA Architectures

The ever-increasing need for more computing and data processing power demands for a continuous and rapid growth of power-hungry data center capacities all over the world. As a first study in 2008 revealed, energy consumption of such data centers is becoming a critical problem, since their power consumption is about to double every 5 years. However, a recently (2016) released follow-up study points out that this threatening trend was dramatically throttled within the past years, due to the increased energy efficiency actions taken by data center operators. Furthermore, the authors of the study emphasize that making and keeping data centers energy-efficient is a continuous task, because more and more computing power is demanded from the same or an even lower energy budget, and that this threatening energy consumption trend will resume as soon as energy efficiency research efforts and its market adoption are reduced. An important class of applications running in data centers are data management systems, which are a fundamental component of nearly every application stack. While those systems were traditionally designed as disk-based databases that are optimized for keeping disk accesses as low a possible, modern state-of-the-art database systems are main memory-centric and store the entire data pool in the main memory, which replaces the disk as main bottleneck. To scale up such in-memory database systems, non-uniform memory access (NUMA) hardware architectures are employed that face a decreased bandwidth and an increased latency when accessing remote memory compared to the local memory. In this thesis, we investigate energy awareness aspects of large scale-up NUMA systems in the context of in-memory data management systems. To do so, we pick up the idea of a fine-grained data-oriented architecture and improve the concept in a way that it keeps pace with increased absolute performance numbers of a pure in-memory DBMS and scales up on NUMA systems in the large scale. To achieve this goal, we design and build ERIS, the first scale-up in-memory data management system that is designed from scratch to implement a data-oriented architecture. With the help of the ERIS platform, we explore our novel core concept for energy awareness, which is Energy Awareness by Adaptivity. The concept describes that software and especially database systems have to quickly respond to environmental changes (i.e., workload changes) by adapting themselves to enter a state of low energy consumption. We present the hierarchically organized Energy-Control Loop (ECL), which is a reactive control loop and provides two concrete implementations of our Energy Awareness by Adaptivity concept, namely the hardware-centric Resource Adaptivity and the software-centric Storage Adaptivity. Finally, we will give an exhaustive evaluation regarding the scalability of ERIS as well as our adaptivity facilities

Proteomic and functional analysis of NCS-1 binding proteins reveals novel signaling pathways required for inner ear development in zebrafish

<p>Abstract</p> <p>Background</p> <p>The semicircular canals, a subdivision of the vestibular system of the vertebrate inner ear, function as sensors of angular acceleration. Little is currently known, however, regarding the underlying molecular mechanisms that govern the development of this intricate structure. Zebrafish represent a particularly tractable model system for the study of inner ear development. This is because the ear can be easily visualized during early embryogenesis, and both forward and reverse genetic techniques are available that can be applied to the discovery of novel genes that contribute to proper ear development. We have previously shown that in zebrafish, the calcium sensing molecule neuronal calcium sensor-1 (NCS-1) is required for semicircular canal formation. The function of NCS-1 in regulating semicircular canal formation has not yet been elucidated.</p> <p>Results</p> <p>We initiated a multistep functional proteomic strategy to identify neuronal calcium sensor-1 (NCS-1) binding partners (NBPs) that contribute to inner ear development in zebrafish. By performing a Y2H screen in combination with literature and database searches, we identified 10 human NBPs. BLAST searches of the zebrafish EST and genomic databases allowed us to clone zebrafish orthologs of each of the human NBPs. By investigating the expression profiles of zebrafish NBP mRNAs, we identified seven that were expressed in the developing inner ear and overlapped with the <it>ncs-1a </it>expression profile. GST pulldown experiments confirmed that selected NBPs interacted with NCS-1, while morpholino-mediated knockdown experiments demonstrated an essential role for <it>arf1</it>, <it>pi4kβ, dan</it>, and <it>pink1 </it>in semicircular canal formation.</p> <p>Conclusion</p> <p>Based on their functional profiles, the hypothesis is presented that Ncs-1a/Pi4kβ/Arf1 form a signaling pathway that regulates secretion of molecular components, including Dan and Bmp4, that are required for development of the vestibular apparatus. A second set of NBPs, consisting of Pink1, Hint2, and Slc25a25, are destined for localization in mitochondria. Our findings reveal a novel signalling pathway involved in development of the semicircular canal system, and suggest a previously unrecognized role for NCS-1 in mitochondrial function via its association with several mitochondrial proteins.</p