Analysis of Residue Probability Density Function and Comparator Offset Error in Pipelined ADCs

This paper presents a new approach to analyze the convergence of residue probability density function (pdf) in pipelined ADCs. Compared to the previous approaches, in the proposed approach, in addition to the analysis of residue pdfs for different input densities, the analysis of the sub-ADC comparator offsets impact on output pdf is possible. Using Fourier analysis, it will be shown that the residue density converges to uniformity. In the half-bit redundant structure, residue pdf concentrates in the center half of the stage full-scale range and 6 dB of extra resolution can be gained. Also, the share of each stage in this resolution improvement is investigated. Examining the sub-ADC threshold offsets impact on residue pdfs, it is observed that with respect to the impact on converter additional resolution, the final stages offset errors are more significant than the first stages offsets

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 $nm$ designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01

Random Number Generation Based on Oscillatory Metastability in Ring Circuits

Random number generator designs are discussed, which utilize oscillatory metastability, induced by switching between two stable states of ring-connected digital gates. For a short time after the switch-over the circuits behave quite randomly, influenced by the circuit noise. We provide simple programs, which simulate the fundamental behavior of our circuits. We also present a mathematical model and theoretical explanations of the underlying physical phenomena, the random phase drift and pulse decay. These also illuminate the principles of other recently published random number generators. The feasibility of the designs was confirmed by FPGA prototypes. These random number generators are small, fast and built of standard logic gates. The simplest example contains just one XOR gate as the source of randomness

Implementation and testing of high-speed CMOS true random number generators based on chaotic systems

We present the design and the validation by means of suitably improved randomness tests of two different implementations of high-performance true-random number generators which use a discrete-time chaotic circuit as their entropy source. The proposed system has been developed from a standard pipeline Analog-to-Digital converter (ADC) design, modified to operate as a set of piecewise-linear chaotic maps. The evolution of each map is observed and quantized to obtain a random bit stream. With this approach it is possible to obtain, on current CMOS technology, a data rate in the order of tens of megabit per second. Furthermore, we can also prove that the design is tamper resistant in the sense that a power analysis cannot leak information regarding the generated bits. This makes the proposed circuit perfectly suitable for embedding in cryptographic systems like smarts cards, even more so if one consider that it could be easily obtained by reconfiguring an existing pipeline ADC. The two prototypes have been designed in a 0.35 um and 0.18 um CMOS technology, and have a throughput of, respectively, 40 Mbit/s and 100 Mbit/s. A comparison between measured results and other high-end commercial solutions shows a comparable quality with a operating speed that is one order of magnitude faster

A Novel Method for increasing the Effective Resolution of High Performance Stochastic Measuring Instruments

Дисертација истражује утицај примене дитерског сигнала (дискретног аналогног униформног шума) генерисаног новом методом на повећање ефективне резолуције мерних инструмената базираних на стохастичкој дигиталној мерној методи. У дисертацији је дат преглед досадашњих решења базираних на стохастичкој дигиталној мерној методи у циљу сагледавања потребе и оправданости истраживања. Предложено решење представља комбинацију псеудослучајног и истински случајног генератора и као такво задржава најбоље особине из обе области. Дaт je прeдлoг нoве методе гeнeрисaњa шумa унифoрмнe рaспoдeлe aмплитудa. Умeстo уoбичajeнoг нaчинa гeнeрисaњa кoришћeњeм гeнeрaтoрa псeудoслучajних брojeвa и Д/А кoнвeртoрa, oвдe сe прeдлaжe гeнeрисaњe зaснoвaнo нa нeунифoрмнoм одабирању тeстeрaстoг или троугаоног нaпoнa. Oсим уштeдe збoг нeкoришћeњa Д/А кoнвeртoрa, дoбит je и мoгућнoст гeнeрисaњa нaпoнa из кoнтинуалнoг, умeстo дискрeтнoг скупa aмплитудa. Вeћинa дaнaшњих хaрдвeрских гeнeрaтoрa псeудoслучajнoг нaпoнa, сe бaзирa нa употреби микрoкoнтрoлeра и Д/A кoнвeртoра, пa je нa тaj нaчин рeзoлуциja гeнeрисaњa псeудoслучajнoг нaпoнa oгрaничeнa резолуцијом Д/A кoнвeрторa. Одабирањем тестерастог или троугаоног напона предложеном методом се остварује готово неограничена резолуција. Употреба овако генерисаног дитерског сигнала доводи до повећања ефективне резолуције код стохастичких мерних инстурмената. Симулацијом је одређена оптимална структура генератора на основу предложене методе. Експериментална мерења су изведена помоћу развијеног прототипа хардверског генератора.Disertacija istražuje uticaj primene diterskog signala (diskretnog analognog uniformnog šuma) generisanog novom metodom na povećanje efektivne rezolucije mernih instrumenata baziranih na stohastičkoj digitalnoj mernoj metodi. U disertaciji je dat pregled dosadašnjih rešenja baziranih na stohastičkoj digitalnoj mernoj metodi u cilju sagledavanja potrebe i opravdanosti istraživanja. Predloženo rešenje predstavlja kombinaciju pseudoslučajnog i istinski slučajnog generatora i kao takvo zadržava najbolje osobine iz obe oblasti. Dat je predlog nove metode generisanja šuma uniformne raspodele amplituda. Umesto uobičajenog načina generisanja korišćenjem generatora pseudoslučajnih brojeva i D/A konvertora, ovde se predlaže generisanje zasnovano na neuniformnom odabiranju testerastog ili trougaonog napona. Osim uštede zbog nekorišćenja D/A konvertora, dobit je i mogućnost generisanja napona iz kontinualnog, umesto diskretnog skupa amplituda. Većina današnjih hardverskih generatora pseudoslučajnog napona, se bazira na upotrebi mikrokontrolera i D/A konvertora, pa je na taj način rezolucija generisanja pseudoslučajnog napona ograničena rezolucijom D/A konvertora. Odabiranjem testerastog ili trougaonog napona predloženom metodom se ostvaruje gotovo neograničena rezolucija. Upotreba ovako generisanog diterskog signala dovodi do povećanja efektivne rezolucije kod stohastičkih mernih insturmenata. Simulacijom je određena optimalna struktura generatora na osnovu predložene metode. Eksperimentalna merenja su izvedena pomoću razvijenog prototipa hardverskog generatora.The dissertation investigates the impact of the application of the dithering signal (discrete analogue uniform noise) generated by the new method for increasing the effective resolution of measurement instruments based on the stochastic digital measurement method. The dissertation provides an overview of the existing solutions based on the stochastic digital measurement method in order to understand the need and justification of the research. The proposed solution represents a combination of a pseudorandom and truly random generator and as such holds the best features in both areas. А suggestion of a new way of generating the noise of the uniform distribution of amplitudes is presented. Instead of the usual way of generating using a pseudorandom number generator and a D/A converter, the generation based on the nonuniform sampling of sawtooth or triangle voltage is proposed. In addition to the savings due to the non-use of a D/A converter, the possibility of generating voltages from a continual instead of a discrete amplitude set is also obtained. Most of today's hardware pseudorandom voltage generators are based on the use of a microcontroller and D/A converter, so in this way the resolution of the pseudorandom voltage generation is limited by the resolution of the D/A converter. By sampling the sawtooth or triangle voltage using the proposed method, almost unlimited resolution is achieved. The use of this generated dither signal leads to an increase in effective resolution in stochastic measuring instruments. The simulation determined the optimal structure of the generator based on the proposed method. Experimental measurements were made using developed hardware

A STANDARDS COMPLIANT ENTROPY SOURCE WITH A FAST ON-THE-FLY ENTROPY DEGRADATION DETECTION AND CORRECTION

Since the advent of technology and world digitalization, most human interaction relies on data exchange through cloud servers on the internet. However, with the innovation also arose concerns about users' privacy and vulnerability. Therefore, cryptography and authentication are essential to protect users' data so only the owner and trusted parties can access it. The security system is the module responsible for securing data inside the devices. The hardware root of trust dwells inside the security system module. True random number generators are the most crucial root of trust devices since they generate the encryption keys. A weak key gives an advantage to an intruder to quickly break the cryptography and steal the data. However, true random number generators are powered by entropy sources susceptible to voltage, temperature, and process variation, which degrades the key entropy. This work proposes an all-digital reconfigurable entropy source with a dual-mode digital processing unit for entropy degradation detection and correction. The processing unit is powered by a subset of statistical tests from the national institute of Standards and Technologies (NIST) and the German Federal Office for Information Security (BSI), which detect and recover the entropy source output entropy within 1.5ms, 15 to 525x faster than similar works. Measured results show that the application specific integrated circuit (ASIC) entropy source yields random bits at a throughput of 1Mb/s with a min-entropy of 0.993 bits at 0.8V. The design consumes up to 42.6μW and occupies an area of 2834μm2 (without the on-chip register bank). Moreover, both the ASIC and the field programable array (FPGA) implementations passed all the NIST and BSI certification testing procedures

Kaos tabanlı hibrit simetrik ve asimetrik şifreleme algoritmaları tasarımı ve uygulaması

06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Bilişim alanında yaşanan hızlı gelişmeler ile birlikte, veri güvenliğinin sağlanması günümüzün en önemli konularından birisi olmuştur. Veri güvenliğinin sağlanması için daha yüksek güvenlik seviyesine sahip aynı zamanda etkin şifreleme sistemlerinin geliştirilmesine çalışılmaktadır. Modern şifreleme algoritmaları özellikle büyük boyutlu veriler ve gerçek zamanlı uygulamalarda ağır işlem yüklerinden dolayı performans kaybına sebep olmaktadır. Kaotik sistemlerin şifreleme tasarımında kullanılması, kaos ve kriptoloji bilimleri arasındaki ilişkinin ortaya konması sonucu ortaya çıkmıştır. Kaotik sistemler sahip olduğu özelliklerden dolayı, kriptolojik uygulamaların temel gereksinimleri olan karıştırma ve yayılma özelliklerini sağlamaktadırlar. Bu tez çalışmasının amacı, kaotik sistemlerin zengin dinamik özellikleri ile modern şifreleme algoritmalarının güçlü yönlerini bir araya getirerek, yüksek güvenlikli ve efektif kaos tabanlı hibrit şifreleme algoritmaları tasarımları gerçekleştirmektir. Tez çalışmasında aşağıdaki temel adımlar gerçekleştirilmiştir: i. Şifreleme çalışmalarında kullanılmak üzere literatürdeki kaotik sistemlere alternatif olarak, iki yeni kaotik sistem (NCS ve skala edilmiş Zhongtang) tasarlanmış ve analizleri yapılmıştır. Yapılan analizler ile yeni sistemlerin zengin dinamik özelliklere ve rasgeleliğe sahip olduğu gösterilmiştir. ii. Yeni geliştirilen kaotik sistemler ile geliştirilecek şifreleme algoritmalarında rasgele sayıların üretimi için iki yeni RSÜ tasarımı yapılmıştır. Yeni RSÜ'lerden elde edilen bit dizilerinin yeterli rasgeleliğe sahip oldukları, NIST 800-22 testleri ile ortaya konmuştur. iii. Blok şifreleme algoritmalarının en önemli bileşenlerinden olan S-Box üretimi için, yeni geliştirilen RSÜ'nün kullanıldığı yeni kaos tabanlı S-Box üretim algoritması geliştirilmiştir. Önerilen S-Box'lar üzerinde performans testleri gerçekleştirilmiştir. S-Box performans test sonuçları literatürdeki kaos tabanlı diğer çalışmalar ile karşılaştırılarak, önerilen S-Box'ların saldırılara karşı daha güçlü ve dayanıklı olduğu gösterilmiştir. iv. RSÜ ve S-Box algoritmalarının tasarımından sonraRSÜ-1 ile kaos tabanlı asimetrik şifreleme algoritması CRSA, RSÜ-2 ve S-Box üretim algoritmaları ile kaos tabanlı simetrik hibrit şifreleme algoritması CS-AES geliştirilmiştir. v. Yeni şifreleme algoritmaları ile resim şifreleme uygulamaları yapılmış ve şifreleme çalışmaları üzerinde güvenlik ve performans analizleri gerçekleştirilmiştir. Geliştirilen hibrit şifreleme algoritmalarının resim şifreleme uygulamalarına ait güvenlik ve performans analiz sonuçları, modern şifreleme algoritmalarının sonuçları ile karşılaştırılarak, saldırılara karşı daha güçlü ve dayanıklı, daha kısa sürede şifreleme gerçekleştiren ve efektif bellek kullanımına sahip oldukları gösterilmiştir

Design of Discrete-time Chaos-Based Systems for Hardware Security Applications

Security of systems has become a major concern with the advent of technology. Researchers are proposing new security solutions every day in order to meet the area, power and performance specifications of the systems. The additional circuit required for security purposes can consume significant area and power. This work proposes a solution which utilizes discrete-time chaos-based logic gates to build a system which addresses multiple hardware security issues. The nonlinear dynamics of chaotic maps is leveraged to build a system that mitigates IC counterfeiting, IP piracy, overbuilding, disables hardware Trojan insertion and enables authentication of connecting devices (such as IoT and mobile). Chaos-based systems are also used to generate pseudo-random numbers for cryptographic applications.The chaotic map is the building block for the design of discrete-time chaos-based oscillator. The analog output of the oscillator is converted to digital value using a comparator in order to build logic gates. The logic gate is reconfigurable since different parameters in the circuit topology can be altered to implement multiple Boolean functions using the same system. The tuning parameters are control input, bifurcation parameter, iteration number and threshold voltage of the comparator. The proposed system is a hybrid between standard CMOS logic gates and reconfigurable chaos-based logic gates where original gates are replaced by chaos-based gates. The system works in two modes: logic locking and authentication. In logic locking mode, the goal is to ensure that the system achieves logic obfuscation in order to mitigate IC counterfeiting. The secret key for logic locking is made up of the tuning parameters of the chaotic oscillator. Each gate has 10-bit key which ensures that the key space is large which exponentially increases the computational complexity of any attack. In authentication mode, the aim of the system is to provide authentication of devices so that adversaries cannot connect to devices to learn confidential information. Chaos-based computing system is susceptible to process variation which can be leveraged to build a chaos-based PUF. The proposed system demonstrates near ideal PUF characteristics which means systems with large number of primary outputs can be used for authenticating devices