Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Characterizationof FD-SOI transistor

In this project, measurements have been made on FD-SOI transistors, fabricated by CEA-LETI, to carry out a characterization of these devices, since they are very new and need to be studied. This work has focused on characterizing the aging mechanism of the devices and the observed RTN. To characterize the aging mechanism and variability of the samples based on the applied cycles, the measurements have been made by applying constant stress voltages (CVS) directly to the device with a wafer prove station and a semiconductor parameter analyzer (SPA). To observe TN, different electrical procedures have been studied, controlling the different parameters during the measurements.En aquest projecte s'han realitzat mesures en transistors FD-SOI, fabricats per CEA-LETI, per tal de dur a terme una caracterització d'aquests dispositius, ja que són molt nous i necessiten de ser estudiats. Aquest treball s'ha centrat en caracteritzar l'envelliment dels dispositius i el RTN observat. Per a caracteritzar l'envelliment i la variabilitat de les mostres en funció dels cicles aplicats, les mesures s'han realitzat aplicant tensions d'estrés constant (CVS) directament al dispositiu amb una taula de puntes i un analitzador de paràmetres de semiconductors (SPA). Per tal d'observar RTN s'han estudiat diferents procediments elèctrics, controlant els diferents paràmetres durant les mesures.En este proyecto se han realizado medidas en transistores FD-SOI, fabricados por CEA-LETI, para llevar a cabo una caracterización de estos dispositivos, puesto que son muy nuevos y necesitan de ser estudiados. Este trabajo se ha centrado en caracterizar los mecanismos de envejecimiento de los dispositivos y el RTN observado. Para caracterizar el envejecimiento y la variabilidad de las muestras en función de los ciclos aplicados, las medidas se han realizado aplicando tensiones de estrés constante (CVS) directamente al dispositivo con una tabla de puntas y un analizador de parámetros de semiconductores (SPA). Para observar RTN se han estudiado diferentes procedimientos eléctricos, controlando los diferentes parámetros durante las medidas

Nano-scale TG-FinFET: Simulation and Analysis

Transistor has been designed and fabricated in the same way since its invention more than four decades ago enabling exponential shrinking in the channel length. However, hitting fundamental limits imposed the need for introducing disruptive technology to take over. FinFET - 3-D transistor - has been emerged as the first successor to MOSFET to continue the technology scaling roadmap. In this thesis, scaling of nano-meter FinFET has been investigated on both the device and circuit levels. The studies, primarily, consider FinFET in its tri-gate (TG) structure. On the device level, first, the main TCAD models used in simulating electron transport are benchmarked against the most accurate results on the semi-classical level using Monte Carlo techniques. Different models and modifications are investigated in a trial to extend one of the conventional models to the nano-scale simulations. Second, a numerical study for scaling TG-FinFET according to the most recent International Technology Roadmap of Semiconductors is carried out by means of quantum corrected 3-D Monte Carlo simulations in the ballistic and quasi-ballistic regimes, to assess its ultimate performance and scaling behavior for the next generations. Ballisticity ratio (BR) is extracted and discussed over different channel lengths. The electron velocity along the channel is analyzed showing the physical significance of the off-equilibrium transport with scaling the channel length. On the circuit level, first, the impact of FinFET scaling on basic circuit blocks is investigated based on the PTM models. 256-bit (6T) SRAM is evaluated for channel lengths of 20nm down to 7nm showing the scaling trends of basic performance metrics. In addition, the impact of VT variations on the delay, power, and stability is reported considering die-to-die variations. Second, we move to another peer-technology which is 28nm FD-SOI as a comparative study, keeping the SRAM cell as the test block, more advanced study is carried out considering the cell‘s stability and the evolution from dynamic to static metrics

Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Fabrication, characterization, and modeling of silicon multi-gate devices

Ph.DDOCTOR OF PHILOSOPH

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level

Nanostructure based devices are very promising candidates for the emerging nanotechnologies with advantage in terms of power consumption and functional density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor (SET) are the focus of this work. The serious challenges faced by the MOSFET due to scaling limits can be solved by these devices. NWFET provides better gate control and overcomes the short channel effects. SET operates in the quantum confinement regime where the basic operation of MOSFET becomes a challenge. SET works better when the dimensions are small encouraging the process of scaling down. Because of these characteristics of the nanodevices, they have achieved a huge interest from the viewpoint of theoretical as well as applied electronics. The studies focus on the understanding of the basic transport characteristics of the devices. The necessity is to develop a model which is efficient, can be used at circuit level and also provides physical insights of the device. The first part of this work focuses on developing the model for SET and to implement it at the circuit level. The transport properties of SET are studied through quantum simulations. The behavioral characterization of the device is performed and the effect of different device parameters on the transport is studied. Furthermore, the impact of gate voltage is analyzed which modulates the current by shifting the energy levels of the device. After observing the transport through SET, a model is developed that efficiently evaluates the IV characteristics of the device. The quantum simulations are used as reference and a huge computational over-head is achieved while maintaining accuracy. Then the model is implemented in hardware descriptive language showing its functional variability at circuit level by designing some logic circuits like AND, OR and FA. In the second part, the performance of the nanoarrays based on NWFET is characterized. A device level model is developed to evaluate the gate capacitance and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices in nanoarray. A nanoarray implementation for bio-sequence alignment based on a systolic array is realized and its essential performance is evaluated. The power consumption, area and performance of the nanoarray implementation are compared with CMOS implementation. A wide solution space can be explored to find the optimal solution trading power and performance and considering the technological limitations of a realistic implementation

Fabricação de protótipos de FinFETs usando métodos alternativos

Orientadores: Leandro Tiago Manera, José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Este trabalho explora métodos alternativos para fabricação de protótipos de FinFETs. Diferentes métodos de definição de fin (fresagem de máscara de Al por feixe de íon focalizado e litografia por feixe focalizado de íons de gálio) são explorados, buscando flexibilidade na definição do número de fins, bem como a altura dos fins. Diferentes estruturas de porta são aplicados nos FinFETs fabricados, com dois materiais dielétricos diferentes (SiON e TiAlON) e dois métodos diferentes para a formação de TiN como eletrodo de porta. O processo de fabricação detalhado é fornecida e discutido, com especial atenção às dificuldades e desafios enfrentados. Etapas de fabricação são cuidadosamente avaliadas, apresentando detalhes e parâmetros de forma que o processo possa ser replicado. Caracterizações morfológicas e elétricas são realizadas nos FinFETs fabricadas. Com a litografia por feixe focalizado de íons de gálio, FinFETs com nove fins em paralelo são fabricados, com largura de fin até 87nm e comportamento elétrico de transistor. Parâmetros elétricos são extraídos, tais como VTH, inclinação de sublimiar, corrente de fuga, mobilidade de portadores, RSD, função trabalho do eletrodo de porta, EOT, e outros. FinFETs com largura fin abaixo de 100nm são apresentados, com inclinação de sublimiar de 120 mV/dec e moblidade de portadores de 372 cm²/V.s, resultados que mostram uma melhoria em relação a trabalhos anteriores, mas ainda deixam espaço para otimizações. Discussões são realizadas, explicando o significado dos parâmetros extraídos, e formas de melhorar os resultados. As diferentes estruturas de porta são avaliados quanto à estabilidade dos parâmetros e densidade de corrente de fuga. Um EOT de 3.6nm é alcançado para o dieléctrico SiON, com densidade de corrente de fuga entre 177uA/cm² e 0.61mA/cm². Desenvolvimentos importantes são feitos no sentido da integração de processos e inovaçoes em termos de métodos de fabricação de protótipos. Trabalhos futuros incluem melhorias na interface de silício-dielétrico e um processo de fabricação auto alinhado para alcançar uma maior transcondutância e acoplamento entre porta e canal, e reduzir a resistência sérieAbstract: This work explores alternative methods for FinFET prototype fabrication. Different fin definition methods (Al hard mask FIB milling and Ga+ FIB lithography) are explored, aiming for flexibility in defining the number of fins, as well as fin height. Alternative gate stacks are applied in the fabricated FinFETs, with two different dielectric materials (SiON and TiAlON) and two different methods for TiN gate electrode formation. The detailed fabrication process is provided and discussed, with special attention to difficulties and challenges faced. Fabrication steps are carefully evaluated, presenting details and parameters such as that the process could be replicated. Morphological and electrical characterizations are performed on the fabricated FinFETs. With the Ga+ FIB lithography method, working FinFETs with nine parallel fins are fabricated, with fin width down to 87nm. Electrical parameters are extracted, such as VTH, subthreshold slope, leakage current, low field mobility, RSD, gate electrode work function, EOT, and others. Working FinFETs with sub-100nm fin width are presented, with subthreshold slope of 120mV/dec and low field mobility of 372cm²/v.s, results that show an improvement on previous works, but still leave room for optimizations. Discussions are performed, explaining the meaning of the extracted parameters, and ways to improve the results. The different gate stacks are evaluated regarding their parameter stability and leakage current density. An EOT of 3.6nm is achieved for the SiON dielectric, with leakage current density between 177uA/cm² and 0.61mA/cm². Important developments have been made towards process integration and novel prototype fabrication methods. Future works include silicon-dielectric interface improvements and a self aligned process to achieve increased transconductance and gate-to-channel coupling, and reduce the series resistanceMestradoEletrônica, Microeletrônica e OptoeletrônicaMestra em Engenharia Elétrica161893/2015-5CNP