Saliency on a chip: a digital approach with an FPGA

Selective-visual-attention algorithms have been successfully implemented in analog VLSI circuits.1 However, in addition to the usual issues of analog VLSI—such as the need to fi ne-tune a large number of biases— these implementations lack the spatial resolution and pre-processing capabilities to be truly useful for image-processing applications. Here we take an alternative approach and implement a neuro-mimetic algorithm for selective visual attention in digital hardware

Glitch-free discretely programmable clock generation on chip

In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling

Towards an on-chip boost switching power converter: a design space exploration

This work presents the design space exploration of a boost switching power converter focused on its monolithic implementation. An analysis in terms of the models of its main circuit elements (switching transistors, inductor, and capacitor) is described. The figure of merit is defined taking into account output voltage ripple, power efficiency, and occupied die area as performance indexes, from which a singular point that maximizes performance is obtained. Transistor-level simulation results for a particular 0.35 mm standard CMOS technology are presented to validate the approach.Peer ReviewedPostprint (published version

A forward body bias generator for digital CMOS circuits with supply voltage scaling

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C

Estimation of Autoregressive Parameters from Noisy Observations Using Iterated Covariance Updates

Estimating the parameters of the autoregressive (AR) random process is a problem that has been well-studied. In many applications, only noisy measurements of AR process are available. The effect of the additive noise is that the system can be modeled as an AR model with colored noise, even when the measurement noise is white, where the correlation matrix depends on the AR parameters. Because of the correlation, it is expedient to compute using multiple stacked observations. Performing a weighted least-squares estimation of the AR parameters using an inverse covariance weighting can provide significantly better parameter estimates, with improvement increasing with the stack depth. The estimation algorithm is essentially a vector RLS adaptive filter, with time-varying covariance matrix. Different ways of estimating the unknown covariance are presented, as well as a method to estimate the variances of the AR and observation noise. The notation is extended to vector autoregressive (VAR) processes. Simulation results demonstrate performance improvements in coefficient error and in spectrum estimation

A Power-Efficient Bio-Potential Acquisition Device with DS-MDE Sensors for Long-Term Healthcare Monitoring Applications

This work describes a power-efficient bio-potential acquisition device for long-term healthcare applications that is implemented using novel microelectromechanical dry electrodes (MDE) and a low power bio-potential processing chip. Using micromachining technology, an attempt is also made to enhance the sensing reliability and stability by fabricating a diamond-shaped MDE (DS-MDE) that has a satisfactory self-stability capability and superior electric conductivity when attached onto skin without any extra skin tissue injury technology. To acquire differential bio-potentials such as ECG signals, the proposed processing chip fabricated in a standard CMOS process has a high common mode rejection ratio (C.M.R.R.) differential amplifier and a 12-bit analog-to-digital converter (ADC). Use of the proposed system and integrate simple peripheral commercial devices can obtain the ECG signal efficiently without additional skin tissue injury and ensure continuous monitoring more than 70 hours with a 400 mAh battery

Improve Image Security Over wireless Sensor Network

The major weaknesses of Wireless Sensor Network is the energy consumption, because the difficult battery replacement or recharge . The energy consume can be regulator by more than one layers. In this paper goals to reduce the energy consume in the physical layer, because the most of the energy consume occurs in the physical layer. This reduce will be achieved via the use of Zigbee transceiver standard at the physical layer with the reduced complexity and lower power consumption than other system used in wireless sensor networks. Furthermore, such use will also enhance energy efficiency and bit error rate of the wireless sensor network. In this paper will apply the chaotic interleaver and chaos encryption to get best encryption (two level encryption) and reducing in time processing and enhancement simulation for bit error rate and peak signal to noise ration by transceiver image cameraman though an AWGN and Rayleigh fadingnbsp channels are displayed

Enhancement of Image Transmission Using Chaotic Interleaver over Wireless Sensor Network

The wireless sensor networks different from classic wired networks, WMSN differs from other scalar network mainly nature and size of data transmitted, memory resources, and power consumption in each node for processing and transmission. The images broadcasting over wireless multimedia sensor networks that can be used in IEEE 802.15.4 (Zig-Bee) for short-range multimedia transmissions. In this paper a strong interleaver mechanism prepared to reduce or immune a burst error of network , this can be done by applying the chaotic interleaving on the pixel, bit ,and chip. The enhancement simulation for bit error rate and peak signal to noise rationnbsp by transceiver image cameraman though AWGN and Rayleigh fadingnbsp channels are displayed. While transmitting the image by 20 dB signal to noise ratio on the Rayleigh fading channel, an improvement on the peak signal to noise ratio of the received image from 25.9 dB to 78.4 dB can be observed