Use of Bilayer gate insulator in GaN-on-Si Vertical Trench MOSFETs : impact on performance and reliability

We propose to use a bilayer insulator (2.5 nm Al2O3 + 35 nm SiO2) as an alternative to a conventional uni-layer Al2O3 (35 nm), for improving the performance and the reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on a test vehicle structure for module development, which has a limited OFF-state performance. We demonstrate that devices with the bilayer dielectric present superior reliability characteristics than those with the uni-layer, including: (i) gate leakage two-orders of magnitude lower; (ii) 11 V higher off-state drain breakdown voltage; and (iii) 18 V higher gate-source breakdown voltage. From Weibull slope extractions, the uni-layer shows an extrinsic failure, while the bilayer presents a wear-out mechanism. Extended reliability tests investigate the degradation process, and hot-spots are identified through electroluminescence microscopy. TCAD simulations, in good agreement with measurements, reflect electric field distribution near breakdown for gate and drain stresses, demonstrating a higher electric field during positive gate stress. Furthermore, DC capability of the bilayer and unilayer insulators are found to be comparable for same bias points. Finally, comparison of trapping processes through double pulsed and V-th transient methods confirms that the V-th shifts are similar, despite the additional interface present in the bilayer devices

Exploring the impact of data breaches and system malfunctions on users’ safety and privacy perceptions in the context of autonomous vehicles

Technological advancements allow for increasingly automated driving systems as well as the large-scale availability of fully autonomous vehicles (AVs) in the future. In this research-in-progress paper, we propose a research concept to further investigate the interplay of users’ perceived privacy risks and trust in AV safety associated with data breaches and system failures. Specifically, we aim to analyze whether system malfunctions impact privacy risk perceptions and whether data breaches impact users’ trust in AV safety by considering the trust in the AV manufacturer. Additionally, we offer first insights into preliminary data and explain our future research intentions. A more detailed understanding of the relationship between privacy and safety trust in the context of AVs could help manufacturers to better direct efforts to compensate for or prevent data breaches and system malfunctions potentially leading to increased user acceptance and technology adoption

Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes

As technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can correct only single bit errors. During the last decade, a number of codes have been developed to correct the emerging error patterns, focusing initially on double adjacent errors and later on three bit burst errors. However, as the memory cells get smaller and smaller, the error patterns created by radiation will continue to change and thus new codes will be needed. In addition, the memory layout and the technology used may also make some patterns more likely than others. For example, in some memories, there maybe elements that separate blocks of bits in a word, making errors that affect two blocks less likely. Finally, for a given memory, depending on the data stored, some error patterns may be more critical than others. For example, if numbers are stored in the memory, in most cases, errors on the more significant bits have a larger impact. Therefore, for a given memory and application, to achieve optimal protection, we would like to have a code that corrects a given set of patterns. This is not possible today as there is a limited number of code choices available in terms of correctable error patterns and word lengths. However, most of the codes used to protect memories are linear block codes that have a regular structure and which design can be automated. In this paper, we propose the automation of error correction code design for memory protection. To that end, we introduce a software tool that given a word length and the error patterns that need to be corrected, produces a linear block code described by its parity check matrix and also the bit placement. The benefits of this automated design approach are illustrated with several case studies. Finally, the tool is made available so that designers can easily produce custom error correction codes for their specific needs.Jiaqiang Li and Liyi Xiao would like to acknowledge the support of the Fundamental Research Funds for the Central Universities (Grant No. HIT.KISTP.201404), Harbin science and innovation research special fund (2015RAXXJ003), and Special found for development of Shenzhen strategic emerging industries (JCYJ20150625142543456). Pedro Reviriego would like to acknowledge the support of the TEXEO project TEC2016-80339-R funded by the Spanish Ministry of Economy and Competitivity and of the Madrid Community research project TAPIR-CM Grant No. P2018/TCS-4496

Novel TCAD Approach for the Investigation of Charge Transport in Thick Amorphous SiO2 Insulators

A TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal-insulator-metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping-detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach

Accelerated Tests on Si and SiC Power Transistors with Thermal, Fast and Ultra-Fast Neutrons

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed

Accelerated tests on Si and SiC power transistors with thermal, fastand ultra-fast neutrons

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Investigation of the Electric Field and Charge Density Distribution of pristine and defective 2D WSe2_2 by Differential Phase Contrast Imaging

Most properties of solid materials are defined by their internal electric field and charge density distributions which so far have been difficult to measure with sufficient spatial resolution. For 2D materials, the electric field at the atomic level in particular influences the optoelectronic properties. In this study, the atomic-scale electric field and charge density distribution of 2D WSe$_2$ are revealed by using an emerging microscopy technique, differential phase contrast (DPC) imaging in the scanning transmission electron microscope (STEM). Combined with high-angle annular dark-field imaging the charge density distribution of bi- and trilayers of WSe$_2$ is mapped. A measured higher positive charge density located at the selenium atomic columns compared to the tungsten atomic columns is reported, and possible reasons are discussed. Furthermore, the change in the electric field distribution of a selenium point defect in a trilayer is investigated exhibiting a characteristic electric field distribution in the vicinity of the defect: there are characteristic regions with locally enhanced and with locally reduced electric field magnitudes compared to the pristine lattice.Comment: 20 pages including the supplementary information, 3 figures in the main part and additional 2 figures in the supplementary informatio

TVS transient behavior modeling method, and system-level effective ESD design for USB3.x interface

This research proposal presents a methodology whereby a protection device can be modeled in SPICE compatible platforms with respect to the transient behaviors during Electrostatic Discharge (ESD) events. This methodology uses an exclusively black-box approach to characterize the parameters of the protection device, thereby allowing it to be implemented without intimate knowledge of the DUT. Results of this methodology can be used to predict the transient response (conductivity modulation and snapback delay) of the ESD protection devices, and thereby predicts how much current could flow into the device (typically a digital IO pin) under protection. The transient behavior modeling methodology for the ESD protection device is developed for the purpose of system level ESD design, and it is part of the study of System-level Effective ESD Design (SEED) methodology. During the work, the transient behavior modeling method and the SEED methodology have been applied to a high-speed USB3.x repeater IC circuit design. This article introduces a PCB test board working as USB3.x repeater, which allows to place various on-board protection devices and to measure the residual voltage and current at the IO pin accurately. In Section 2, the transient behavior modeling framework and the characterization method will be introduced. The validation results of three different types of protection devices are shown in the end of the section. In Section 3, the implementation of SEED methodology to a USB3.x system design will be introduced. The measurement setup is described in detail. Finally, the validation results for different scenarios will be shown --Abstract, page iii