5G NR-밴드 무선 주파수 송수신기의 검증을 위한 모델링 방법

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2021.8. 김재하.도래한 초연결시대에서는 스마트폰뿐만 아니라 다양한 사물 인터넷 디바이스들이 5세대 이동통신 시스템을 활용하면서, 늘어난 데이터량과 트래픽을 감당하기 위해 밀리미터파 대역의 사용이 필수적일 것이다. 시스템이 보다 대용량화 그리고 광대역화 됨에 따라, 통신 규약을 만족시키기 위해, 점차 거대한 디지털 캘리브레이션 및 신호처리 로직이, 무선 통신 전단부 칩에 함께 집적되고 있다. 따라서 멀티-도메인의 신호(아날로그/디지털/무선통신 신호)가 복잡하게 혼성된 무선통신 집적회로 칩을, 짧은 개발 기간 동안 충분히 검증하기엔 어려움이 따른다. 일반적으로 혼성 신호 시스템을 검증하기 위해서는, 하위 시스템을 모두 포함해서 시간 도메인의 시뮬레이션을 수행해야 하는데, 이를 위한 스파이스와 스파이스-하드웨어 기술 언어의 co-시뮬레이션은 지나치게 느리다는 한계가 있기 때문이다. 따라서, 멀티-도메인의 신호를 빠르고 정확하게 시뮬레이션 가능하게 하는 모델링 방법과, 다양한 시나리오의 검증 완성도를 향상시켜줄 있는 검증 기술이 모두 요구된다. 혼성 시스템을 검증하기 위해서는, 아날로그와 무선 통신 블록들을 시스템 베릴로그 상에서 구현된 함수적 모델로 대체하고, 디지털 블록들과 함께 하나의 디지털 플랫폼에서 시뮬레이션하는 것이 효과적이다. 실제 설계할 때, 문제가 되는 대부분의 에러들은, 연결 오류, 부호 오류, 신호 순서 오류, 혹은 잘못된 파워 도메인과의 연결과 같이 사소한 오류들이다. 이러한 오류를 찾기 위해, 오래 걸리는 트랜지스터-레벨의 시뮬레이션을 수행하기보다는, 아날로그 스파이스 모델들을 시스템 베릴로그 모델들로 대체하고, 보다 다양한 시나리오를 빠르게 검증하는 방법이 검증 완성도를 향상시키는데 적합하다. 그럼에도, 지나치게 단순한 선형 모델이나, 중요한 회로 특성이 빠진 모델로는 원하는 수준의 검증이 불가능할 수 있다. 예를 들어, 직접 변조 구조의 무선통신 송수신기에서 발생하는 비이상 효과, 저전력 동작을 하면서 발생하는 비선형 효과, 그리고 흔히 메모리 효과는 모델에 효과를 충분히 반영해 주어야만, 주파수 도메인에서의 검증, 성능 예측 등의 검증을 의미 있게 수행할 수 있다. 문제는 비선형 시스템은 훨씬 복잡한 식으로 표현되며, 시뮬레이션 시 연산량도 크게 늘어나기 때문에, 비선형 모델을 만들고 시뮬레이션 하기가 쉽지 않다는 것이다. 따라서 모델이 비이상성들을 충분히 반영하면서도 효과적인 검증을 가능하게 하는 모델링/시뮬레이션 방법 역시 요구된다. 본 학위 논문에서는, 무선통신 송수신기 집적회로 전체의 모사 모델을 제안한다. 모델은 누설 신호와 신호 간 불일치에 의한 비-이상적인 효과를 엑스모델의 알고리즘을 활용해 반영하였고, 비선형성과 메모리 효과를 볼테라-섭동법을 활용해 반영하였다. 제안하는 모델은 다양한 주파수 대역과 동작 모드를 검증하는데, 기존 등가 베이스밴드 모델보다 30~1800배 빠르게 시뮬레이션 할 수 있었고, 비이상 효과에 대해, 통신 성능들(심볼의 오류 벡터의 크기, 인접 채널의 파워 그리고 비트 에러)을 평가 가능했다. 나아가, 아날로그 검사기를 활용한 기능 검증법과 모델 파라미터 커버리지 분석법을 적용하여, 시스템-레벨 검증의 완성도를 향상시켰다. 무선통신 집적회로 모델에 다양한 디자인/파라미터 오류를 주입하고, 시뮬레이션 동안 검사기가 찾은 에러의 개수와 커버리지 결과를 실험적으로 보였다.In mobile RF transceiver systems, the large number of digital circuits employed to compensate or calibrate the non-idealities of the RF circuits call for models that can work within the digital verification platform, such as SystemVerilog. While baseband-equivalent real-number models (RNMs) are the current state-of-the-art for modeling RF transceivers in SystemVerilog, their simulation speeds and accuracy are not adequate predicting performance degradation. Since, its signals can only model the frequency components near the carrier frequency but not the DC offsets or high-order harmonic effects arising due to nonlinearities. Therefore, the growing impacts of nonlinearities call for nonlinear modeling of their key components to predict the overall system's performance. This dissertation presents the models for a multi-standard, direct-conversion RF transceiver for evaluating its system-level performance and verifying its digital controllers. Also, this work demonstrates the Volterra series model for the nonlinear analysis of a low-noise amplifier circuit in SystemVerilog, leveraging the functional expression and event-driven simulation capability of XMODEL. The simulation results indicate that the presented models, including the digital configuration/calibration logic for the 5G sub-6GHz-band and mmWave-band transceiver, can deliver 30–1800× higher speeds than the baseband-equivalent RNMs while estimating the quadrature amplitude modulation signal constellation and error vector magnitude in the presence of non-idealities such as nonlinearities, DC offsets, and I/Q imbalances. In addition, it implements functionality checkers and parameter coverage analysis to advance the completeness of system-level verification of the RF transceivers model.Chapter 1. Introduction 1 1.1 Design and Verification Flow . 1.2 5G NR Band RF Transceiver IC . 1.3 Baseband-Equivalent and Passband Modeling . 1.4 Thesis Organization . Chapter 2. Modeling and Simulation of RF Transceiver 11 2.1 Direct Conversion RF Transceiver . 2.2 Proposed Transceiver Models . 2.3 System and Simulation Performance . Chapter 3. Nonlinear RF System Modeling 28 3.1 Volterra / Perturbation Method . 3.2 Low Noise Amplifier Example . 3.3 Nonlinearity Analysis . Chapter 4. Coverage Analysis and Functional Verification 42 4.1 Model Parameter Coverage Analysis . 4.2 Self-Checking Testbench . Chapter 5. Conclusion 54 Appendix 55 A.1 Trigonometric Equation for Non-Ideal Effects . A.2 RNM Baseband Equivalent Modeling . A.3 Parameter Coverage Analysis . A.4 List of Models . Bibliography 63 Abstract in Korean 66석

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Design of Power-Efficient Optical Transceivers and Design of High-Linearity Wireless Wideband Receivers

The combination of silicon photonics and advanced heterogeneous integration is promising for next-generation disaggregated data centers that demand large scale, high throughput, and low power. In this dissertation, we discuss the design and theory of power-efficient optical transceivers with System-in-Package (SiP) 2.5D integration. Combining prior arts and proposed circuit techniques, a receiver chip and a transmitter chip including two 10 Gb/s data channels and one 2.5 GHz clocking channel are designed and implemented in 28 nm CMOS technology. An innovative transimpedance amplifier (TIA) and a single-ended to differential (S2D) converter are proposed and analyzed for a low-voltage high-sensitivity receiver; a four-to-one serializer, programmable output drivers, AC coupling units, and custom pads are implemented in a low-power transmitter; an improved quadrature locked loop (QLL) is employed to generate accurate quadrature clocks. In addition, we present an analysis for inverter-based shunt-feedback TIA to explicitly depict the trade-off among sensitivity, data rate, and power consumption. At last, the research on CDR-based​ clocking schemes for optical links is also discussed. We introduce prior arts and propose a power-efficient clocking scheme based on an injection-locked phase rotator. Next, we analyze injection-locked ring oscillators (ILROs) that have been widely used for quadrature clock generators (QCGs) in multi-lane optical or wireline transceivers due to their low power, low area, and technology scalability. The asymmetrical or partial injection locking from 2 phases to 4 phases results in imbalances in amplitude and phase. We propose a modified frequency-domain analysis to provide intuitive insight into the performance design trade-offs. The analysis is validated by comparing analytical predictions with simulations for an ILRO-based QCG in 28 nm CMOS technology. This dissertation also discusses the design of high-linearity wireless wideband receivers. An out-of-band (OB) IM3 cancellation technique is proposed and analyzed. By exploiting a baseband auxiliary path (AP) with a high-pass feature, the in-band (IB) desired signal and out-of-band interferers are split. OB third-order intermodulation products (IM3) are reconstructed in the AP and cancelled in the baseband (BB). A 0.5-2.5 GHz frequency-translational noise-cancelling (FTNC) receiver is implemented in 65nm CMOS to demonstrate the proposed approach. It consumes 36 mW without cancellation at 1 GHz LO frequency and 1.2 V supply, and it achieves 8.8 MHz baseband bandwidth, 40dB gain, 3.3dB NF, 5dBm OB IIP3, and −6.5dBm OB B1dB. After IM3 cancellation, the effective OB-IIP3 increases to 32.5 dBm with an extra 34 mW for narrow-band interferers (two tones). For wideband interferers, 18.8 dB cancellation is demonstrated over 10 MHz with two −15 dBm modulated interferers. The local oscillator (LO) leakage is −92 dBm and −88 dB at 1 GHz and 2 GHz LO respectively. In summary, this technique achieves both high OB linearity and good LO isolation

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

Recursive receiver down-converters with multiband feedback and gain-reuse for low-power applications

Power minimization in wireless transceivers has become increasingly critical in recent years with the emergence of standards for short-distance applications in the 900 MHz and 2.4 GHz industrial, scientific and medical (ISM) radio bands. The demand for long battery life and better portability in such applications has led to extensive research on low power radio architectures. This dissertation introduces receiver topologies for low-power systems and presents a theoretical performance analysis of the topologies. Two fully integrated receiver down-converters that demonstrate the concept are implemented in a 0.13-[mu]m CMOS technology. These topologies employ merged mixers and IF amplifiers in order to reduce power dissipation for a given dynamic range performance. In the described topologies, the input stage of a mixer is used to simultaneously provide conversion gain and baseband amplification. This is achieved by applying the down-converted IF signal to input of the mixer. Consequently, the effective conversion gain of the design is greatly enhanced with current requirement primarily determined by the input transconductor. Potential degradation mechanisms related to instability and second-order distortion are identified and solved by the use of appropriate circuit techniques. Noise and linearity performance of the down-converters is analyzed and compared to that of conventional cascaded design counterparts. The potential for enhancement of IIP3 performance through cancellation of nonlinear products is discussed. Potential extensions of the above work including feedback-based architectures that exploit multiple loops for further maximizing the power efficiency of receiver front-ends are also presented.Electrical and Computer Engineerin

A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

High-Performance Multi-Antenna Wireless for 5G and Beyond

Over the next decade, multi-antenna radios, including phased array and multiple-input-multiple-output (MIMO) radios, are expected to play an essential role in the next-generation of wireless networks. Phased arrays can reject spatial interferences and provide coherent beamforming gain, and MIMO technology promises to significantly enhance the system performance in the coverage, capacity, and user data rate through the beamforming or diversity/capacity gain which can substantially increase the range in wireless links, that are challenged from the transmitter (TX) power handling, receiver (RX) noise perspectives and a multi-path environment. Furthermore, the multi-user MIMO (MU-MIMO) can simultaneously serve multiple users which is vital for femtocell base stations and access points (AP). Full-duplex (FD) wireless, namely simultaneous transmission and reception at the same frequency, is an emerging technology that has gained attention due to its potential to double the data throughput, as well as provide other benefits in the higher layers such as better spectral efficiency, reducing network and feedback signaling delays, and resolving hidden-node problems to avoid collisions. However, several challenges remain in the quest for the high-performance integrated FD radios. Transmitter power handling remains an open problem, particularly in FD radios that integrate a shared antenna interface. Secondly, FD operation must be achieved across antenna VSWR variations and a changing EM environment. Finally, FD must be extended to multi-antenna radios, including phased array and multi-input multi-output (MIMO) radios, as over the next decade, they are expected to play an essential role in the next generation of wireless networks. Multi-antenna FD operation, however, is challenged not only by the self-interference (SI) from each TX to its own RX but also cross-talk SI (CT-SI) between antennas. In this dissertation, first, a full-duplex phased array circulator-RX (circ.-RX) is proposed that achieves self-interference cancellation (SIC) through repurposing beamforming degrees of freedom (DoF) on TX and RX. Then, an FD MIMO circ.-RX is proposed that achieves SI and CT-SI cancellation (CT-SIC) through passive RF and shared-delay baseband (BB) canceller that addresses challenges associated with FD MIMO operation. Wireless radios at millimeter-wave (mm-wave) frequencies enable the high-speed link for portable devices due to the wide-band spectrum available. Large-scale arrays are required to compensate for high path loss to form an mm-wave link. Mm-wave MIMO systems with digitization enable virtual arrays for radar, digital beamforming (DBF) for high mobility scenarios and spatial multiplexing. To preserve MIMO information, the received signal from each element in MIMO RX should be transported to ADC/DSP IC for DBF, and vice versa on the TX side. A large-scale array can be formed by tiling multiple mm-wave IC front-ends, and thus, a single-wire interface is desired between DSP IC and mm-wave ICs to reduce board routing complexity. Per-element digitization poses the challenge of handling high data-rate I/O in large-scale tiled MIMO mm-wave arrays. SERializer – DESerializer (SERDES) is traditionally being used as a high-speed link in computing systems and networks. However, SERDES results in a large area and power consumption. In this dissertation, a 60~GHz 4-element MIMO TX with a single-wire interface is presented that de-multiplexes the baseband signal of all elements and LO reference that are frequency-domain multiplexed on a single-wire coax cable

Auxiliary-Path-Assisted Digital Linearization of Wideband Wireless Receivers

Wireless communication systems in recent years have aimed at increasing data rates by ensuring flexible and efficient use of the radio spectrum. The dernier cri in this field has been in the area of carrier aggregation and cognitive radio. Carrier aggregation is a major component of LTE-Advanced. With carrier aggregation, a number of separate LTE carriers can be combined, by mobile network operators, to increase peak data rates and overall network capacity. Cognitive radios, on the other hand, allow efficient spectrum usage by locating and using spatially vacant spectral bands. High monolithic integration in these application fields can be achieved by employing receiver architectures such as the wideband direct conversion receiver topology. This is advantageous from the view point of cost, power consumption and size. However, many challenges exist, of particular importance is nonlinear distortion arising from analog front-end components such as low noise amplifiers (LNA). Nonlinear distortions especially become severe when several signals of varying amplitudes are received simultaneously. In such cases, nonlinear distortions stemming from strong signals may deteriorate the reception of the weaker signals, and also impair the receiver’s spectrum sensing capabilities. Nonlinearity, usually a consequence of dynamic range limitation, degrades performance in wideband multi-operator communications systems, and it will have a notable role in future wireless communication system design. This thesis presents a digital domain linearization technique that employs a very nonlinear auxiliary receiver path for nonlinear distortion cancellation. The proposed linearization technique relies on one-time adaptively-determined linearization coefficients for cancelling nonlinear distortions. Specifically, we take a look at canceling the troublesome in-band third order intermodulation products using the proposed technique. The proposed technique can be extended to cancel out both even and higher order odd intermodulation products. Dynamic behavioral models are used to account for RF nonlinearities, including memory effects which cannot be ignored in the wideband scenario. Since the proposed linearization technique involves the use of two receiver paths, techniques for correcting phase delays between the two paths are also introduced. Simplicity is the hallmark of the proposed linearization technique. It can achieve up to +30 dBm in IIP3 performance with ADC resolution being a major performance bottleneck. It also shows strong tolerance to strong blocker nonlinearities