Machine-Learning Attacks on PolyPUFs, OB-PUFs, RPUFs, LHS-PUFs, and PUF–FSMs

A physically unclonable function (PUF) is a circuit of which the input–output behavior is designed to be sensitive to the random variations of its manufacturing process. This building block hence facilitates the authentication of any given device in a population of identically laid-out silicon chips, similar to the biometric authentication of a human. The focus and novelty of this work is the development of efficient impersonation attacks on the following five Arbiter PUF–based authentication protocols: (1) the so-called PolyPUF protocol of Konigsmark, Chen, and Wong, as published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2016, (2) the so-called OB-PUF protocol of Gao, Li, Ma, Al-Sarawi, Kavehei, Abbott, and Ranasinghe, as presented at the IEEE conference PerCom 2016, (3) the so-called RPUF protocol of Ye, Hu, and Li, as presented at the IEEE conference AsianHOST 2016, (4) the so-called LHS-PUF protocol of Idriss and Bayoumi, as presented at the IEEE conference RFID-TA 2017, and (5) the so-called PUF–FSM protocol of Gao, Ma, Al-Sarawi, Abbott, and Ranasinghe, as published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2018. The common flaw of all five designs is that the use of lightweight obfuscation logic provides insufficient protection against machine learning attacks

Extended class of linear feedback shift registers

Shift registers with linear feedback are frequently used. They owe their popularity to very well developed theoretical base. Registers with feedback of prime polynomials are of particular practical importance. They are willingly applied as test sequence generators and test response compactors. The article presents an attempt to extend the class of registers with linear feedback. Basing on the formal description of the register, the algorithms of register transformation are proposed. It allows to obtain the registers with equivalent graphs.[1] I. Gosciniak, “Linear Registers with Mixed Feedback, in Polish; Rejestry liniowe z mieszanym sprzȩżeniem zwrotnym,” Pomiary Automatyka Kontrola, no. 1, pp. 4–6, 1996.[2] K. Iwasaki, “Analysis and proposal of signature circuits for LSI testing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 84–90, 1988.[3] L.-T. Wang, N. Touba, R. Brent, H. Xu, and H. Wang, “On Designing Transformed Linear Feedback Shift Registers with Minimum Hardware Cost – Technical Report,” Computer Engineering Research Center Department of Electrical & Computer Engineering The University of Texas at Austin, 2011.[4] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Method for Synthesizing Linear Finite State Machines,” U.S. Patent, No. 6,353,842, 2002.[5] I. Gosciniak, “Equivalent Form of Linear Feedback Shift Registers,” in XIXth National Conference Circuit Theory and Eletronic Networks, 1996, pp. 115–120.[6] L. Alaus, D. Noguet, and J. Palicot, “A Reconfigurable LFSR for Tristandard SDR Transceiver, Architecture and Complexity Analysis,” in Digital System Design Architectures, Methods and Tools, 2008. DSD ’08. 11th EUROMICRO Conference on. IEEE Computer Society, 2008, pp. 61–67.[7] R. Ash, Information Theory. John Wiley & Sons, 1967.[8] M. Kopec, “Can Nonlinear Compactors Be Better than Linear Ones?” IEEE Trans. Comput., no. 11, pp. 1275–1282, 1995.[9] A. Gucha and L. Kinney, “Relating the Cyclic Behaviour of Linear Intrainverted Feedback shift Registers,” IEEE Transactions on Computers, vol. 41, no. 9, pp. 1088–1100, 1992

XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference

Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to conventional deep neural networks at a fraction of the cost in terms of memory and energy. In this paper, we introduce the XNOR Neural Engine (XNE), a fully digital configurable hardware accelerator IP for BNNs, integrated within a microcontroller unit (MCU) equipped with an autonomous I/O subsystem and hybrid SRAM / standard cell memory. The XNE is able to fully compute convolutional and dense layers in autonomy or in cooperation with the core in the MCU to realize more complex behaviors. We show post-synthesis results in 65nm and 22nm technology for the XNE IP and post-layout results in 22nm for the full MCU indicating that this system can drop the energy cost per binary operation to 21.6fJ per operation at 0.4V, and at the same time is flexible and performant enough to execute state-of-the-art BNN topologies such as ResNet-34 in less than 2.2mJ per frame at 8.9 fps.Comment: 11 pages, 8 figures, 2 tables, 3 listings. Accepted for presentation at CODES'18 and for publication in IEEE Transactions on Computer-Aided Design of Circuits and Systems (TCAD) as part of the ESWEEK-TCAD special issu