Robustness of TAP-based Scan Networks

It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks

Conception et test des circuits et systèmes numériques à haute fiabilité et sécurité

Research activities I carried on after my nomination as Chargé de Recherche deal with the definition of methodologies and tools for the design, the test and the reliability of secure digital circuits and trustworthy manufacturing. More recently, we have started a new research activity on the test of 3D stacked Integrated CIrcuits, based on the use of Through Silicon Vias. Moreover, thanks to the relationships I have maintained after my post-doc in Italy, I have kept on cooperating with Politecnico di Torino on the topics related to test and reliability of memories and microprocessors.Secure and Trusted DevicesSecurity is a critical part of information and communication technologies and it is the necessary basis for obtaining confidentiality, authentication, and integrity of data. The importance of security is confirmed by the extremely high growth of the smart-card market in the last 20 years. It is reported in "Le monde Informatique" in the article "Computer Crime and Security Survey" in 2007 that financial losses due to attacks on "secure objects" in the digital world are greater than $11 Billions. Since the race among developers of these secure devices and attackers accelerates, also due to the heterogeneity of new systems and their number, the improvement of the resistance of such components becomes today’s major challenge.Concerning all the possible security threats, the vulnerability of electronic devices that implement cryptography functions (including smart cards, electronic passports) has become the Achille’s heel in the last decade. Indeed, even though recent crypto-algorithms have been proven resistant to cryptanalysis, certain fraudulent manipulations on the hardware implementing such algorithms can allow extracting confidential information. So-called Side-Channel Attacks have been the first type of attacks that target the physical device. They are based on information gathered from the physical implementation of a cryptosystem. For instance, by correlating the power consumed and the data manipulated by the device, it is possible to discover the secret encryption key. Nevertheless, this point is widely addressed and integrated circuit (IC) manufacturers have already developed different kinds of countermeasures.More recently, new threats have menaced secure devices and the security of the manufacturing process. A first issue is the trustworthiness of the manufacturing process. From one side, secure devices must assure a very high production quality in order not to leak confidential information due to a malfunctioning of the device. Therefore, possible defects due to manufacturing imperfections must be detected. This requires high-quality test procedures that rely on the use of test features that increases the controllability and the observability of inner points of the circuit. Unfortunately, this is harmful from a security point of view, and therefore the access to these test features must be protected from unauthorized users. Another harm is related to the possibility for an untrusted manufacturer to do malicious alterations to the design (for instance to bypass or to disable the security fence of the system). Nowadays, many steps of the production cycle of a circuit are outsourced. For economic reasons, the manufacturing process is often carried out by foundries located in foreign countries. The threat brought by so-called Hardware Trojan Horses, which was long considered theoretical, begins to materialize.A second issue is the hazard of faults that can appear during the circuit’s lifetime and that may affect the circuit behavior by way of soft errors or deliberate manipulations, called Fault Attacks. They can be based on the intentional modification of the circuit’s environment (e.g., applying extreme temperature, exposing the IC to radiation, X-rays, ultra-violet or visible light, or tampering with clock frequency) in such a way that the function implemented by the device generates an erroneous result. The attacker can discover secret information by comparing the erroneous result with the correct one. In-the-field detection of any failing behavior is therefore of prime interest for taking further action, such as discontinuing operation or triggering an alarm. In addition, today’s smart cards use 90nm technology and according to the various suppliers of chip, 65nm technology will be effective on the horizon 2013-2014. Since the energy required to force a transistor to switch is reduced for these new technologies, next-generation secure systems will become even more sensitive to various classes of fault attacks.Based on these considerations, within the group I work with, we have proposed new methods, architectures and tools to solve the following problems:• Test of secure devices: unfortunately, classical techniques for digital circuit testing cannot be easily used in this context. Indeed, classical testing solutions are based on the use of Design-For-Testability techniques that add hardware components to the circuit, aiming to provide full controllability and observability of internal states. Because crypto‐ processors and others cores in a secure system must pass through high‐quality test procedures to ensure that data are correctly processed, testing of crypto chips faces a dilemma. In fact design‐for‐testability schemes want to provide high controllability and observability of the device while security wants minimal controllability and observability in order to hide the secret. We have therefore proposed, form one side, the use of enhanced scan-based test techniques that exploit compaction schemes to reduce the observability of internal information while preserving the high level of testability. From the other side, we have proposed the use of Built-In Self-Test for such devices in order to avoid scan chain based test.• Reliability of secure devices: we proposed an on-line self-test architecture for hardware implementation of the Advanced Encryption Standard (AES). The solution exploits the inherent spatial replications of a parallel architecture for implementing functional redundancy at low cost.• Fault Attacks: one of the most powerful types of attack for secure devices is based on the intentional injection of faults (for instance by using a laser beam) into the system while an encryption occurs. By comparing the outputs of the circuits with and without the injection of the fault, it is possible to identify the secret key. To face this problem we have analyzed how to use error detection and correction codes as counter measure against this type of attack, and we have proposed a new code-based architecture. Moreover, we have proposed a bulk built-in current-sensor that allows detecting the presence of undesired current in the substrate of the CMOS device.• Fault simulation: to evaluate the effectiveness of countermeasures against fault attacks, we developed an open source fault simulator able to perform fault simulation for the most classical fault models as well as user-defined electrical level fault models, to accurately model the effect of laser injections on CMOS circuits.• Side-Channel attacks: they exploit physical data-related information leaking from the device (e.g. current consumption or electro-magnetic emission). One of the most intensively studied attacks is the Differential Power Analysis (DPA) that relies on the observation of the chip power fluctuations during data processing. I studied this type of attack in order to evaluate the influence of the countermeasures against fault attack on the power consumption of the device. Indeed, the introduction of countermeasures for one type of attack could lead to the insertion of some circuitry whose power consumption is related to the secret key, thus allowing another type of attack more easily. We have developed a flexible integrated simulation-based environment that allows validating a digital circuit when the device is attacked by means of this attack. All architectures we designed have been validated through this tool. Moreover, we developed a methodology that allows to drastically reduce the time required to validate countermeasures against this type of attack.TSV- based 3D Stacked Integrated Circuits TestThe stacking process of integrated circuits using TSVs (Through Silicon Via) is a promising technology that keeps the development of the integration more than Moore’s law, where TSVs enable to tightly integrate various dies in a 3D fashion. Nevertheless, 3D integrated circuits present many test challenges including the test at different levels of the 3D fabrication process: pre-, mid-, and post- bond tests. Pre-bond test targets the individual dies at wafer level, by testing not only classical logic (digital logic, IOs, RAM, etc) but also unbounded TSVs. Mid-bond test targets the test of partially assembled 3D stacks, whereas finally post-bond test targets the final circuit.The activities carried out within this topic cover 2 main issues:• Pre-bond test of TSVs: the electrical model of a TSV buried within the substrate of a CMOS circuit is a capacitance connected to ground (when the substrate is connected to ground). The main assumption is that a defect may affect the value of that capacitance. By measuring the variation of the capacitance’s value it is possible to check whether the TSV is correctly fabricated or not. We have proposed a method to measure the value of the capacitance based on the charge/ discharge delay of the RC network containing the TSV.• Test infrastructures for 3D stacked Integrated Circuits: testing a die before stacking to another die introduces the problem of a dynamic test infrastructure, where test data must be routed to a specific die based on the reached fabrication step. New solutions are proposed in literature that allow reconfiguring the test paths within the circuit, based on on-the-fly requirements. We have started working on an extension of the IEEE P1687 test standard that makes use of an automatic die-detection based on pull-up resistors.Memory and Microprocessor Test and ReliabilityThanks to device shrinking and miniaturization of fabrication technology, performances of microprocessors and of memories have grown of more than 5 magnitude order in the last 30 years. With this technology trend, it is necessary to face new problems and challenges, such as reliability, transient errors, variability and aging.In the last five years I’ve worked in cooperation with the Testgroup of Politecnico di Torino (Italy) to propose a new method to on-line validate the correctness of the program execution of a microprocessor. The main idea is to monitor a small set of control signals of the processors in order to identify incorrect activation sequences. This approach can detect both permanent and transient errors of the internal logic of the processor.Concerning the test of memories, we have proposed a new approach to automatically generate test programs starting from a functional description of the possible faults in the memory.Moreover, we proposed a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success

Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1)

Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e SistemasO Boundary Scan consiste numa infra-estrutura de teste por varrimento periférico, com o objectivo de garantir a controlabilidade e observabilidade dos principais inputs e outputs dos vários circuitos integrados que compõem uma placa de circuito impresso. Esta metodologia está, desde 1990, normalizada pelo Institute of Electrical and Electronics Engineers como o IEEE 1149.1, que permite a implementação facilitada de sistemas de teste integrados em placas de circuitos digitais. O presente trabalho incide no estudo da tecnologia, abordando-se a sua motivação, importante presença na indústria para a aplicação de testes estruturais, descrição técnica detalhada, e metodologias para o seu controlo; e o desenvolvimento de um controlador compatível capaz de actuar as infra-estruturas de Boundary Scan. O controlador de Boundary Scan, aliado ao software desenvolvido, deverá possibilitar o teste de placas que suportem a tecnologia, garantindo a sua observação e controlo, estando adequado a uma utilização numa vertente didáctica. Outras funcionalidades com o intuito de melhor explorarem as capacidades do teste ou controlo por Boundary Scan, ou melhorar a sua utilidade como ferramenta no ensino de electrónica, foram também consideradas. A adaptação do sistema ao presente contexto tecnológico foi garantida pela análise de produtos comerciais e de distribuição livres, actualmente disponíveis. O sistema desenvolvido é composto por três componentes: O controlador de Boundary Scan e o seu firmware; a biblioteca dinâmica para o seu controlo; e a aplicação gráfica que serve de interface com o utilizador. Esta modularidade do sistema permite que o controlador e biblioteca de controlo possam ser facilmente integrados em outros projectos, com outro software desenvolvido para o seu controlo. A aplicação gráfica criada disponibiliza um conjunto de ferramentas genéricas que tiram partido da tecnologia de Boundary Scan, destacando-se: Controlo e monitorização dos pinos físicos dos componentes alvo; Pesquisa e identificação automática dos componentes do circuito alvo; Programação de microcontroladores Atmel ATmega; Execução de código de descrição de testes segundo os standards Serial Vector Format (SVF) e Xilinx Serial Vector Format (XSVF); Aplicação automática ou manual de instruções de teste; entre outras. O suporte à linguagem Serial Vector Format permite que o controlador seja eficientemente utilizado para o teste de circuitos, ou em parceria com um grande número de softwares de desenvolvimento, na execução de tarefas por Boundary Scan (utilizando os ficheiros Serial Vector Format que estes criam). O protótipo funcional desenvolvido foi testado com recurso a uma placa de teste desenhada para o efeito, composta por um conjunto de componentes que dispõem de infra-estrutura de testes em conformidade com a norma IEEE 1149.1, que serve de alvo para o controlador. O teste ao sistema permitiu validar o correcto funcionamento das funcionalidades implementadas e optimizar o seu desempenho. Considera-se que o controlador proposto respondeu às expectativas tanto no que respeita à sua funcionalidade, que excedeu os objectivos inicialmente traçados, de controlo e observação das placas alvo; como relativamente ao seu desempenho, que, pelo menos, enquadrado numa utilização didáctica, se entende muito satisfatório.The Boundary Scan is a test architecture with the aim of granting access to the input and output pins of the various components of an electric digital circuit, allowing for its observability and controllability. This technology was standardized, in the year 1990, by the Institute of Electrical and Electronics Engineers, as IEEE 1149.1, which describes the implementation of the boundary scan as an integrated test system used for testing and debugging printed circuit boards. The present work focus on the study the IEEE 1149.1 standard; understanding its motivation and important role in the industry in the structural testing of electronic products; describing a detailed technical overview including its control methods; and the development of a compatible controller for testing and debugging of circuit boards through the boundary scan interface. The designed Boundary Scan controller, with its control software, should be able to test circuits with Boundary Scan capabilities, assuring its controllability and observability, while being suitable for use in a didactic environment. Other functionalities in order to better explore the Boundary Scan technology, or enhance its use as a tool for electronic teaching, were also considered. To better suit the developed controller to the current technology context, other commercially or freely available controllers were researched and taken in consideration. The designed system has three main components: The boundary scan controller and its firmware, which links the computer to the target circuit board; a dynamic library for easier control; and the computer application that serves as the graphic user interface. This system modularity allows for an easy integration of the controller and library in other projects. The graphic application, as it was developed, has a number of generic applications that take advantage of Boundary Scan technology: Control and monitoring of the physical inputs/outputs pins of the target components; Automatic search and identification of the individual components of the target circuitry; Programming of Atmel Atmega microcontrollers; Execution of test descriptive languages according to Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) specification; Manual or automatic application of test instructions; among others. The Serial Vector Format support enables the controller to be efficiently used for circuit testing, or to work in conjunction with a great number of development software, executing boundary scan operations by interpreting their Serial Vector Format files. The assembled functional prototype of the controller was tested with a test board created for that purpose, which integrate a number of integrated circuit components compatible with the IEEE 1149.1, to be used as the target during the system testing. The conducted tests validated the correct functioning of the implemented functionalities and allowed to optimize its performance. Considering the initial objectives of the project, the proposed controller responded well to both expectations regarding to its functionality, which far surpassed the initially proposed set, for controlling and observing the target boards; and with respect to its performance, that, at least as far as a didactic use is concerned, is considered very satisfactory