Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

AUTOMATED WRAPPER DESIGN FOR ISCAS ’89 BENCHMARK CIRCUITS

System-on-chip (SOC) enables the reuse of existing IP blocks in a system, thereby making it possible to design complex systems within a short period of time. With the complexity of the design comes the problem of testing the SOC. A typical SOC can integrate many modules, therefore making it difficult to test these individual modules by accessing from the primary interfaces of the chip. To aleviate this test access issue for SOC‟s, the IEEE 1500 standard has been introduced. There are commercial tools from main EDA players such as Synopsys that can help with the insertion of the IEEE 1500 wrapper. However, most researchers have no access to the expensive tool. Even if they do, the tools are protected so they do not allow researchers access to the internal features to explore potential enhancements. There is no open source tools that can assist test researchers with the 1500 wrapper insertion. In this thesis, we illustrate our effort at automating the IEEE 1500 wrapper insertion. The design of the IEEE 1500 wrapper is done in Verilog and the automation is done using the Perl scripting language. The inserted wrapper modules are validated and an efficient approach of executing wrapper external tests is also illustrated in this thesis

Platform-based design, test and fast verification flow for mixed-signal systems on chip

This research is providing methodologies to enhance the design phase from architectural space exploration and system study to verification of the whole mixed-signal system. At the beginning of the work, some innovative digital IPs have been designed to develop efficient signal conditioning for sensor systems on-chip that has been included in commercial products. After this phase, the main focus has been addressed to the creation of a re-usable and versatile test of the device after the tape-out which is close to become one of the major cost factor for ICs companies, strongly linking it to model’s test-benches to avoid re-design phases and multi-environment scenarios, producing a very effective approach to a single, fast and reliable multi-level verification environment. All these works generated different publications in scientific literature. The compound scenario concerning the development of sensor systems is presented in Chapter 1, together with an overview of the related market with a particular focus on the latest MEMS and MOEMS technology devices, and their applications in various segments. Chapter 2 introduces the state of the art for sensor interfaces: the generic sensor interface concept (based on sharing the same electronics among similar applications achieving cost saving at the expense of area and performance loss) versus the Platform Based Design methodology, which overcomes the drawbacks of the classic solution by keeping the generality at the highest design layers and customizing the platform for a target sensor achieving optimized performances. An evolution of Platform Based Design achieved by implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform is therefore presented. ISIF is a highly configurable mixed-signal chip which allows designers to perform an effective design space exploration and to evaluate directly on silicon the system performances avoiding the critical and time consuming analysis required by standard platform based approach. In chapter 3 we describe the design of a smart sensor interface for conditioning next generation MOEMS. The adoption of a new, high performance and high integrated technology allow us to integrate not only a versatile platform but also a powerful ARM processor and various IPs providing the possibility to use the platform not only as a conditioning platform but also as a processing unit for the application. In this chapter a description of the various blocks is given, with a particular emphasis on the IP developed in order to grant the highest grade of flexibility with the minimum area occupation. The architectural space evaluation and the application prototyping with ISIF has enabled an effective, rapid and low risk development of a new high performance platform achieving a flexible sensor system for MEMS and MOEMS monitoring and conditioning. The platform has been design to cover very challenging test-benches, like a laser-based projector device. In this way the platform will not only be able to effectively handle the sensor but also all the system that can be built around it, reducing the needed for further electronics and resulting in an efficient test bench for the algorithm developed to drive the system. The high costs in ASIC development are mainly related to re-design phases because of missing complete top-level tests. Analog and digital parts design flows are separately verified. Starting from these considerations, in the last chapter a complete test environment for complex mixed-signal chips is presented. A semi-automatic VHDL-AMS flow to provide totally matching top-level is described and then, an evolution for fast self-checking test development for both model and real chip verification is proposed. By the introduction of a Python interface, the designer can easily perform interactive tests to cover all the features verification (e.g. calibration and trimming) into the design phase and check them all with the same environment on the real chip after the tape-out. This strategy has been tested on a consumer 3D-gyro for consumer application, in collaboration with SensorDynamics AG

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System on a Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitance nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

Design of electronic systems for automotive sensor conditioning

This thesis deals with the development of sensor systems for automotive, mainly targeting the exploitation of the new generation of Micro Electro-Mechanical Sensors (MEMS), which achieve a dramatic reduction of area and power consumption but at the same time require more complexity in the sensor conditioning interface. Several issues concerning the development of automotive ASICs are presented, together with an overview of automotive electronics market and its main sensor applications. The state of the art for sensor interfaces design (the generic sensor interface concept), consists in sharing the same electronics among similar sensor applications, thus saving cost and time-to-market but also implementing a sub-optimal system with area and power overheads. A Platform Based Design methodology is proposed to overcome the limitations of generic sensor interfaces, by keeping the platform generality at the highest design layers and pursuing the maximum optimization and performances in the platform customization for a specific sensor. A complete design flow is presented (up to the ASIC implementation for gyro sensor conditioning), together with examples regarding IP development for reuse and low power optimization of third party designs. A further evolution of Platform Based Design has been achieved by means of implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform. ISIF is a highly programmable mixed-signal chip which allows a substantial reduction of design space exploration time, as it can implement in a short time a wide class of sensor conditioning architectures. Thus it lets the designers evaluate directly on silicon the impact of different architectural choices, as well as perform feasibility studies, sensor evaluations and accurate estimation of the resulting dedicated ASIC performances. Several case studies regarding fast prototyping possibilities with ISIF are presented: a magneto-resistive position sensor, a biosensor (which produces pA currents in presence of surface chemical reactions) and two capacitive inertial sensors, a gyro and a low-g YZ accelerometer. The accelerometer interface has also been implemented in miniboards of about 3 cm2 (with ISIF and sensor dies bonded together) and a series of automatic trimming and characterization procedures have been developed in order to evaluate sensor and interface behaviour over the automotive temperature range, providing a valuable feedback for the implementation of a dedicated accelerometer interface

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

This paper reports on the design and implementation of an open-source library of parameterizable and reusable Hardware Description Language (HDL) Intellectual Property (IP) cores designed for the development of Software-Defined Radio (SDR) applications that are deployed on FPGA-based reconfigurable computing platforms. The library comprises a set of cores that were chosen, together with their parameters and interfacing schemas, based on recommendations from industry and academic SDR experts. The operation of the SDR cores is first validated and then benchmarked against two other cores libraries of a similar type to show that our cores do not take much more logic elements than existing cores and that they support a comparable maximum clock speed. Finally, we propose our design for a Domain-Specific Language (DSL) and supporting tool-flow, which we are in the process of building using our SDR library and the Delite DSL framework. We intend to take this DSL and supporting framework further to provide a rapid prototyping system for SDR application development to programmers not experienced in HDL coding. We conclude with a summary of the main characteristics of our SDR library and reflect on how our DSL tool-flow could assist other developers working in SDR field