CAD methodologies for low power and reliable 3D ICs

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin; Committee Member: Mukhopadhyay, Saiba

A Comprehensive Study of the Hardware Trojan and Side-Channel Attacks in Three-Dimensional (3D) Integrated Circuits (ICs)

Three-dimensional (3D) integration is emerging as promising techniques for high-performance and low-power integrated circuit (IC, a.k.a. chip) design. As 3D chips require more manufacturing phases than conventional planar ICs, more fabrication foundries are involved in the supply chain of 3D ICs. Due to the globalized semiconductor business model, the extended IC supply chain could incur more security challenges on maintaining the integrity, confidentiality, and reliability of integrated circuits and systems. In this work, we analyze the potential security threats induced by the integration techniques for 3D ICs and propose effective attack detection and mitigation methods. More specifically, we first propose a comprehensive characterization for 3D hardware Trojans in the 3D stacking structure. Practical experiment based quantitative analyses have been performed to assess the impact of 3D Trojans on computing systems. Our analysis shows that advanced attackers could exploit the limitation of the most recent 3D IC testing standard IEEE Standard 1838 to bypass the tier-level testing and successfully implement a powerful TSV-Trojan in 3D chips. We propose an enhancement for IEEE Standard 1838 to facilitate the Trojan detection on two neighboring tiers simultaneously. Next, we develop two 3D Trojan detection methods. The proposed frequency-based Trojan-activity identification (FTAI) method can differentiate the frequency changes induced by Trojans from those caused by process variation noise, outperforming the existing time-domain Trojan detection approaches by 38% in Trojan detection rate. Our invariance checking based Trojan detection method leverages the invariance among the 3D communication infrastructure, 3D network-on-chips (NoCs), to tackle the cross-tier 3D hardware Trojans, achieving a Trojan detection rate of over 94%. Furthermore, this work investigates another type of common security threat, side-channel attacks. We first propose to group the supply voltages of different 3D tiers temporally to drive the crypto unit implemented in 3D ICs such that the noise in power distribution network (PDN) can be induced to obfuscate the original power traces and thus mitigates correlation power analysis (CPA) attacks. Furthermore, we study the side-channel attack on the logic locking mechanism in monolithic 3D ICs and propose a logic-cone conjunction (LCC) method and a configuration guideline for the transistor-level logic locking to strengthen its resilience against CPA attacks

Susceptibility Predictions of ICs to EMI and Validation of Stochastic EM fields Coupling with a Bespoke RF IC Detector

This research addresses electromagnetic interference (EMI) challenges at high frequencies by developing an advanced methodology to estimate the probability of susceptibility of Integrated Circuits (ICs). The objective is to develop an advanced methodology for estimating the probability of susceptibility of ICs or components on a printed circuit board (PCB) to EMI by statistically characterizing the power absorbed by electronic circuits and enhancing power balance (PWB) methods for enclosures and internal components. The IC EMC standard IEC 62132-4, enables the assessment of susceptibility of an IC by determining the forward power required to induce a malfunction at each pin. This work enhances the previously developed numerical model by incorporating PCB losses, which enables us to estimate the distribution of coupled forward power at the package pin over a number of stirrer positions in a reverberant field. Based on these insights, the research establishes a methodology for predicting the probability of susceptibility of ICs, provided that the component's susceptibility level, transmission line parameters, and the loading of the attached track are known. This work also validates the numerical model through the design and testing of an instrumented custom-designed radio frequency integrated circuit (RF IC) detector, capable of measuring coupled power at its package pin via test PCB tracks. Building upon previous knowledge of PWB methods, using the purpose-built RF IC detector we introduced an enhanced PWB method capable of incorporating the influence of average absorption cross-section (AACS) of the IC at package pins and connected PCB tracks, along with other relevant AACS for internal components within the enclosure. The in-depth consideration of AACS of the components such as PCB tracks and ICs on the device under test, is an upgrade to previously developed PWB methods

Ready to Roll?: Overview of Challenges and Opportunities

Alternative Fuel Vehicles (AFVs) use combinations of vehicle fuels and technologies to reduce the use of petroleum in on-road vehicles. These include low-carbon fuels (sometimes blended with petroleum), electricity, and hybrid technologies combining internal combustion engines with electric motors. DVRPC's Ready to Roll? Report provides an overview for policymakers and citizens in the Greater Philadelphia region about the challenges and opportunities for expanded use of alternative fuel vehicles. The AFVs covered in this report include those most widely available today or likely to become available in the next 10 to 20 years

Preclinical Assessment of HIV Vaccines and Microbicides by Repeated Low-Dose Virus Challenges

BACKGROUND: Trials in macaque models play an essential role in the evaluation of biomedical interventions that aim to prevent HIV infection, such as vaccines, microbicides, and systemic chemoprophylaxis. These trials are usually conducted with very high virus challenge doses that result in infection with certainty. However, these high challenge doses do not realistically reflect the low probability of HIV transmission in humans, and thus may rule out preventive interventions that could protect against “real life” exposures. The belief that experiments involving realistically low challenge doses require large numbers of animals has so far prevented the development of alternatives to using high challenge doses. METHODS AND FINDINGS: Using statistical power analysis, we investigate how many animals would be needed to conduct preclinical trials using low virus challenge doses. We show that experimental designs in which animals are repeatedly challenged with low doses do not require unfeasibly large numbers of animals to assess vaccine or microbicide success. CONCLUSION: Preclinical trials using repeated low-dose challenges represent a promising alternative approach to identify potential preventive interventions

An Electric-Circuit Model on the Inter-Tape Contact Resistance and Current Sharing for REBCO Cable and Magnet Applications

REBCO coated conductor has demonstrated high current capacity that can enable high-field magnets for high energy physics and fusion applications. However, quench protection is still one of the main challenges to be addressed for these applications. In addition, Ic and n value variations along the length of REBCO tapes exist in commercial production. The inter-tape contact resistance plays a key role to develop the self protection capability in cables and magnets by enabling current sharing and suppressing excessive eddy currents. Here we propose an electric-circuit model to describe the inter-tape contact resistance and its impact on the current sharing between REBCO tapes. We report the experiments on a 2-stacked tape REBCO cable with local Ic drop to validate the model. With the developed model, we study the upper limit of the contact resistance which allows current sharing between tapes. We also study the impact of variation in Ic and n values in tapes on the cable performance. Our model is expected to provide useful insight into the current sharing and target values for inter-tape contact resistance in REBCO cables and magnets for various applications