Design of a hysteresis predictive control strategy with engineering application cases

Aplicat embargament des de la data de defensa fins al 31 de juliol de 2022This doctoral thesis exposes the development of a redesigned Predictive Control strategy that uses hysteresis to improve the performance of the controlled systems in different fields of application. The approach may use one of the three hysteresis models presented in this thesis. Moreover, the hysteresis may be used as a modulation stage or as a reference trajectory generator. The first step in the methodology of this research will be to validate the hysteresis dynamic model that will be used within the control scheme. Due to the three exposed hysteresis models have the same constitution , it is assumed that the test of one is enough to guarantee the validation of the other two hysteresis systems. This validation consists on implementing the hysteresis model in an experimental platform to confirm that the model is indeed feasible. Later, it will be seen that this application is within the scope of renewable energies. Once the hysteresis model is validated, the proposed strategy is developed. This is an Adaptive-Predictive control scheme with a modulation stage for the control signal. This stage employs hysteresis to improve the functioning of the adaptive phase and in general the entire closed-loop performance. lt will be shown how the use of this modulation scenario salves the parametric drift problem commonly present in some adaptive based controlled systems. Additionally, a fault detection system within the Adaptive-Predictive control scheme is also proposed and validated through a numerical simulation. Furthermore, it will be seen how the hysteresis also can be used as a model to generate the reference trajectory needed to accomplish the control objective. Finally, the proposed strategy is implemented in a varied set of control systems to validate it. These control systems are: a nonlinear Van der Poi oscillator, a nonlinear base-isolated system, a DC-DC buck converter, and a single-phase inverter.Esta tesis doctoral expone el desarrollo de una estrategia de Control Predictivo rediseñada que utiliza histéresis para mejorar el rendimiento de los sistemas controlados en diferentes campos de aplicación. Este esquema de control puede utilizar uno de los tres sistemas de histéresis presentados en esta tesis. Además, la histéresis se puede utilizar como etapa de modulación o como generador de trayectorias de referencia. El primer paso en la metodología de esta investigación será validar el modelo dinámico de histéresis que se utilizará dentro del esquema de control. Debido a que los tres modelos de histéresis expuestos tienen la misma constitución, se asume que la prueba de uno es suficiente para garantizar la validación de los otros dos modelos de histéresis. Esta validación consiste en implementar el modelo de histéresis en una plataforma experimental para confirmar que este es realmente factible. Posteriormente, se verá que esta aplicación está dentro del ámbito de las energias renovables. Una vez validado el modelo de histéresis, se desarrolla la estrategia propuesta. Es decir, un esquema de control Adaptativo-Predictivo con una etapa de modulación para la señal de control. Esta etapa emplea histéresis para mejorar el funcionamiento de la fase adaptativa y, en general, de todo el rendimiento del sistema en lazo cerrado. Se mostrará cómo el uso de este etapa de modulación resuelve el problema de la deriva paramétrica comúnmente presente en algunos sistemas basados en control adaptativo. Adicionalmente, también se propone y valida un sistema de detección de fallos dentro del esquema de control Adaptativo-Predictivo mediante una simulación numérica. Además, se verá cómo la histéresis también se puede utilitzar como modelo para generar la trayectoria de referencia necesaria para lograr el objetivo de control. Finalmente, la estrategia propuesta se implementa en un conjunto variado de sistemas de control para validarla. Estos sistemes de control son: un oscilador Van der Poi no lineal, un sistema no lineal de base aisladora, un convertidor Buck DC-DC y un inversor monofásico.Postprint (published version

System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters

abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques

In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power

Seismic Resilience-based Design and Optimization: A Deep Learning and Cyber-Physical Approach

With the growing acceptance and better understanding of the importance of uncertainties in seismic design, traditional design approaches with deterministic analysis are being replaced with more reliable approaches within a risk-based context. Recently, resilience has been increasingly studied as a comprehensive metric to assess the ability of a system to withstand and recover from disturbances with large uncertainties. For civil infrastructure systems susceptible to natural hazards, especially earthquakes as considered herein, seismic resilience could provide a measurement integrating both earthquake and post-earthquake performance. For structural engineers, improving infrastructure disaster resilience starts with the design of more resilient structures. This requires a quantitative approach to explicitly guild the design towards better resilience. However, when attempting to quantify the seismic resilience of a structure, large uncertainties lead to large computational costs associated with risk-based approaches. Additionally, the accuracy of numerical simulations under wide range of design scenarios is unknown. To address these challenges, this dissertation investigates the role of seismic resilience in structural design. This dissertation starts with a novel seismic protective device to improve structural resilience and follows with the development of a quantitative and efficient design, evaluation, and optimization framework for seismic resilience. This framework proposes metamodeling through deep neural networks for improved efficiency and cyber-physical systems for improved accuracy. Feedforward neural networks are adopted for fragility metamodeling, while online learning long-short term memory neural networks are developed for structural component metamodeling. Real-time hybrid simulation is used for the construction of cyber-physical systems. The proposed framework is demonstrated to have both improved accuracy and significantly reduced computational/experimental cost when compared to existing approaches. The applicability of the framework is illustrated through the optimization of structural systems for improved seismic resilience

Design and test of digitally-controlled power management IPs in advanced CMOS technologies

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35 m: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35 m CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility.VILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF

ATS-6 engineering performance report. Volume 2: Orbit and attitude controls

Attitude control is reviewed, encompassing the attitude control subsystem, spacecraft attitude precision pointing and slewing adaptive control experiment, and RF interferometer experiment. The spacecraft propulsion system (SPS) is discussed, including subsystem, SPS design description and validation, orbital operations and performance, in-orbit anomalies and contingency operations, and the cesium bombardment ion engine experiment. Thruster failure due to plugging of the propellant feed passages, a major cause for mission termination, are considered among the critical generic failures on the satellite