An Automated Design-flow for FPGA-based Sequential Simulation

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

Preparing sparse solvers for exascale computing.

Sparse solvers provide essential functionality for a wide variety of scientific applications. Highly parallel sparse solvers are essential for continuing advances in high-fidelity, multi-physics and multi-scale simulations, especially as we target exascale platforms. This paper describes the challenges, strategies and progress of the US Department of Energy Exascale Computing project towards providing sparse solvers for exascale computing platforms. We address the demands of systems with thousands of high-performance node devices where exposing concurrency, hiding latency and creating alternative algorithms become essential. The efforts described here are works in progress, highlighting current success and upcoming challenges. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

Customisable arithmetic hardware designs

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Analyzing UVM reuse

Abstract. This thesis investigates Universal Verification Methodology’s (UVM) reuse possibilities. Initally, the object-oriented features of the UVM’s programming language SystemVerilog (SV), are introduced. Those features are one enabling factor in UVM reuse. The work also provides a brief overview to the development history of UVM and presents its properties. The structure of a conventional UVM testbench is also demonstrated. Finally, the features that make the UVM testbench more reusable are briefly introduced. In the practical part of the study, a UVM testbench is made for Nordic Semiconductor’s Introproject. The testbench was created with extensive comments so that beginners would get the most out of it. The methods that make the testbench reusable are also applied to the testbench. At the end of the practical part, the reuse possibilities of the testbench were tested by changing the Design Under Test (DUT). Modifications were made to the testbench in order to match the new features of the DUT.UVM uudelleenkäytön analysointi. Tiivistelmä. Tämä diplomityö tutkii Universaalin varmennusmenetelmän (UVM) uudelleenkäyttömahdollisuuksia. Aluksi UVM:n ohjelmointikielen, SystemVerilogin olio-ohjelmointipohjaisia ominaisuuksia käydään läpi. Nämä ominaisuudet ovat yksi mahdollistava tekijä UVM uudelleenkäytössä. Työssä tehdään lisäksi lyhyt katsaus UVM:n kehityshistoriaan ja esitellään myös sen ominaisuudet sekä tavanomaisen UVM-testipenkin rakenne. Lopuksi esitellään lyhyesti ominaisuuksia, jolla saa tehtyä UVM testipenkistä paremmin uudelleenkäytettävän. Työn käytännön osuudessa tehdään UVM-testipenkki Nordic Semiconductorin Introprojektiin. Testipenkki tehtiin laajasti kommentoimalla, jotta aloitteleva testipenkin tekijä saa siitä mahdollisimman paljon irti. Testipenkin tekemisessä käytettiin myös menetelmiä, joita esiteltiin aiemmassa teoriakappaleessa. Käytännön osuuden lopuksi testattiin testipenkin uudelleenkäyttöä muuttamalla testissä olevaa komponenttia. Testipenkkiin tehtiin muutokset, jolla se saatiin taas vastaamaan komponentin tarpeita

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks