In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

Blumink, R.

Holzenspies, P.K.F.

Rutgers, J.H.

Smit, Gerardus Johannes Maria

Westmijze, M.

Wolkotte, P.T.

English

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress

NARCIS 

An Automated Design-flow for FPGA-based Sequential Simulation

Abstract—In this paper we describe the automated design flow that will transform and map a given homogeneous or hetero-geneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress. I

Pascal T. Wolkotte

Jochem H. Rutgers

Philip K. F. Hölzenspies

Mark Westmijze

Remco Blumink

Gerard J. M. Smit

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An automated design-flow for fpga-based sequential simulation

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An Automated Design-flow for FPGA-based Sequential Simulation

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University of Twente Research Information