Characterisation of thermal and coupling effects in advanced silicon MOSFETs

PhD ThesisNew approaches to metal-oxide-semiconductor field effect transistor (MOSFET) engineering emerge in order to keep up with the electronics market demands. Two main candidates for the next few generations of Moore’s law are planar ultra-thin body and buried oxide (UTBB) devices and three-dimensional FinFETs. Due to miniature dimensions and new materials with low thermal conductivity, performance of advanced MOSFETs is affected by self-heating and substrate effects. Self-heating results in an increase of the device temperature which causes mobility reduction, compromised reliability and signal delays. The substrate effect is a parasitic source and drain coupling which leads to frequency-dependent analogue behaviour. Both effects manifest themselves in the output conductance variation with frequency and impact analogue as well as digital performance. In this thesis self-heating and substrate effects in FinFETs and UTBB devices are characterised, discussed and compared. The results are used to identify trade-offs in device performance, geometry and thermal properties. Methods how to optimise the device geometry or biasing conditions in order to minimise the parasitic effects are suggested. To identify the most suitable technique for self-heating characterisation in advanced semiconductor devices, different methods of thermal characterisation (time and frequency domain) were experimentally compared and evaluated alongside an analytical model. RF and two different pulsed I-V techniques were initially applied to partially depleted silicon-on-insulator (PDSOI) devices. The pulsed I-V hot chuck method showed good agreement with the RF technique in the PDSOI devices. However, subsequent analysis demonstrated that for more advanced technologies the time domain methods can underestimate self-heating. This is due to the reduction of the thermal time constants into the nanosecond range and limitations of the pulsed I-V set-up. The reduction is related to the major increase of the surface to volume ratio in advanced MOSFETs. Consequently the work showed that the thermal properties of advanced semiconductor devices must be characterised within the frequency domain. For UTBB devices with 7-8 nm Si body and 10 nm ultra-thin buried oxide (BOX) the analogue performance degradation caused by the substrate effects can be stronger than the analogue performance degradation caused by self-heating. However, the substrate effects can be effectively reduced if the substrate doping beneath the buried ii oxide is adjusted using a ground plane. In the MHz – GHz frequency range the intrinsic voltage gain variation is reduced ~6 times when a device is biased in saturation if a ground plane is implemented compared with a device without a ground plane. UTBB devices with 25 nm BOX were compared with UTBB devices with 10 nm BOX. It was found that the buried oxide thinning from 25 nm to 10 nm is not critical from the thermal point of view as other heat evacuation paths (e.g. source and drain) start to play a role. Thermal and substrate effects in FinFETs were also analysed. It was experimentally shown that FinFET thermal properties depend on the device geometry. The thermal resistance of FinFETs strongly varies with the fin width and number of parallel fins, whereas the fin spacing is less critical. The results suggest that there are trade-offs between thermal properties and integration density, electrostatic control and design complexity, since these aspects depend on device geometry. The high frequency substrate effects were found to be effectively reduced in devices with sub-100 nm wide fins.Engineering and Physical Sciences Research Council (EPSRC) and EU fundin

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V

Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Heating Effects in Nanoscale Devices

Non

Electrical and Thermal Transport in Alternative Device Technologies

abstract: The goal of this research work is to develop a particle-based device simulator for modeling strained silicon devices. Two separate modules had to be developed for that purpose: A generic bulk Monte Carlo simulation code which in the long-time limit solves the Boltzmann transport equation for electrons; and an extension to this code that solves for the bulk properties of strained silicon. One scattering table is needed for conventional silicon, whereas, because of the strain breaking the symmetry of the system, three scattering tables are needed for modeling strained silicon material. Simulation results for the average drift velocity and the average electron energy are in close agreement with published data. A Monte Carlo device simulation tool has also been employed to integrate the effects of self-heating into device simulation for Silicon on Insulator devices. The effects of different types of materials for buried oxide layers have been studied. Sapphire, Aluminum Nitride (AlN), Silicon dioxide (SiO2) and Diamond have been used as target materials of interest in the analysis and the effects of varying insulator layer thickness have also been investigated. It was observed that although AlN exhibits the best isothermal behavior, diamond is the best choice when thermal effects are accounted for.Dissertation/ThesisM.S. Electrical Engineering 201

Proposed Thermal Circuit Model for the Cost Effective Design of Fin FET

The Complementary metal-oxide-semiconductor (CMOS) device has been rapidly evolving and its size has been drastically decreasing ever since it was first fabricated in 1960 [Us Patent 3,356,858: 1967]. The substantial reduction in the CMOS device size has led to short channel effects which have resulted in the introduction of Fin Field Effect Transistor (FinFET), a tri-gate transistor built on a silicon on insulator (SOI) substrate. Furthermore, due to the geometry of the FinFET the severity of the heating problem has dramatically increased. Self-heating in the 3-dimensional FinFET device enhances the temperature gradients and peak temperature, which decrease drive current, increase the interconnect delays and degrade the device and interconnect reliability. In this work we have proposed a methodology to develop an accurate thermal model for the FinFET through a rigorous physics-based mathematical approach. A thermal circuit for the FinFET will be derived from the model. This model will allow chip designers to predict interconnect temperature which will lead them to achieve cost-effective design for the FinFET-based semiconductor chips. Keywords: Bulk CMOS, SOI CMOS, FinFET, Thermal heating

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Improvement of a nano-scale silicon on insulator field effect transistor performance using electrode, doping and buried oxide engineering

In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce the device leakage current and controlling the threshold voltage, a p-type retrograde doping is introduced into channel region. Since the air has the least permittivity among materials, it can be utilized to decrease the device parasitic capacitances. Based on this, an air gap is embedded in the buried oxide near the silicon to improve RF performance of the device. Because the source and drain electrodes are embedded in and over the silicon film in the source and drain regions, we called this structure EEIOS-SOI MOSFET. “EEIOS” stands for “Embedded Electrodes In and Over the Silicon film”. During this work, EEIOS-SOI MOSFET is compared with a conventional SOI MOSFET and another SOI MOSFET with just Embedded Electrodes In the Silicon Film (EEIS-SOI). EEIS-SOI presents better electrical figure of merits including lower subthreshold slope and lower leakage current in simulations. An immense investigation among these devices shows that EEIOS-SOI MOSFET has better transconductance, lower gate injection leakage current and lower temperature related to DC parameters and higher cut off frequency, gain bandwidth product and unilateral power gain related to AC figures of merits compared to its counterparts

Improvement of a nano-scale silicon on insulator field effect transistor performance using electrode, doping and buried oxide engineering

In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a silicon region has embedded in the buried oxide. In order to reduce the device leakage current and controlling the threshold voltage, a p-type retrograde doping is introduced into channel region. Since the air has the least permittivity among materials, it can be utilized to decrease the device parasitic capacitances. Based on this, an air gap is embedded in the buried oxide near the silicon to improve RF performance of the device. Because the source and drain electrodes are embedded in and over the silicon film in the source and drain regions, we called this structure EEIOS-SOI MOSFET. “EEIOS” stands for “Embedded Electrodes In and Over the Silicon film”. During this work, EEIOS-SOI MOSFET is compared with a conventional SOI MOSFET and another SOI MOSFET with just Embedded Electrodes In the Silicon Film (EEIS-SOI). EEIS-SOI presents better electrical figure of merits including lower subthreshold slope and lower leakage current in simulations. An immense investigation among these devices shows that EEIOS-SOI MOSFET has better transconductance, lower gate injection leakage current and lower temperature related to DC parameters and higher cut off frequency, gain bandwidth product and unilateral power gain related to AC figures of merits compared to its counterparts