Multimedia Networks: Fundamentals and Future Directions

Multimedia has become an integral part of computing and communications environment, and networks are carrying ever-increasing volume of multimedia information. The main characteristics of multimedia information are high-volume and bursty traffic, with low tolerance to delay and delay variance. The legacy networks (designed in 70s and 80s) are not able to meet these requirements. Enhancements to the older networking technologies have been developed to convert these into multimedia networks. Enhancements to LANs include Switched Ethernet, Isochronous Ethernet, Fast Ethernet, 100VGAnyLAN, FDDI-II, and Synchronous FDDI. WAN options for multimedia networking include digital leased lines and ISDN. The Internet has revolutionized business and personal communications, but falls short of being a genuine multimedia network. To make the Internet capable of carrying multimedia traffic, new protocols such as MBone, ST-II, RTP, and RSVP have been developed. Internet2 is a new initiative that is aimed at overcoming the problems of throughput, delay and jitter encountered on the original Internet. One technology that was developed with multimedia networking as one of its main applications, is the Asynchronous Transfer Mode (ATM) technology. Upcoming Gigabit Ethernet technology will provide a path for upgrading current Ethernet networks into multimedia networks

Application of MPLS-TP for transporting power system protection data

Power utilities are increasingly dependent on the use of communications networks. These networks are evolving to be packet-based, rather than using conventional Time-Division Multiplexing (TDM) technologies. Transporting current differential protection traffic over a packet network is especially challenging, due to the safety-critical nature of protection, the strict requirements for low delay and low asymmetrical delay, and the extensive use of legacy TDM-based protocols. This paper highlights the key technical characteristics of Multi-Protocol Label Switching-Transport Profile (MPLS-TP), and demonstrates its application for transporting current differential protection traffic. A real-time hardware-in-the-loop testing approach has been used to thoroughly validate the technologies in various configurations. It is demonstrated that MPLS-TP technologies can meet the requirements of current differential protection and other, less critical applications. In particular, it is shown that delay and asymmetrical delay can be controlled through the inherent use of bi-directional paths---even when “hitless” link redundancy is configured. The importance of appropriate traffic engineering, clocking schemes, circuit emulation methods is also demonstrated

Co-design of Security Aware Power System Distribution Architecture as Cyber Physical System

The modern smart grid would involve deep integration between measurement nodes, communication systems, artificial intelligence, power electronics and distributed resources. On one hand, this type of integration can dramatically improve the grid performance and efficiency, but on the other, it can also introduce new types of vulnerabilities to the grid. To obtain the best performance, while minimizing the risk of vulnerabilities, the physical power system must be designed as a security aware system. In this dissertation, an interoperability and communication framework for microgrid control and Cyber Physical system enhancements is designed and implemented taking into account cyber and physical security aspects. The proposed data-centric interoperability layer provides a common data bus and a resilient control network for seamless integration of distributed energy resources. In addition, a synchronized measurement network and advanced metering infrastructure were developed to provide real-time monitoring for active distribution networks. A hybrid hardware/software testbed environment was developed to represent the smart grid as a cyber-physical system through hardware and software in the loop simulation methods. In addition it provides a flexible interface for remote integration and experimentation of attack scenarios. The work in this dissertation utilizes communication technologies to enhance the performance of the DC microgrids and distribution networks by extending the application of the GPS synchronization to the DC Networks. GPS synchronization allows the operation of distributed DC-DC converters as an interleaved converters system. Along with the GPS synchronization, carrier extraction synchronization technique was developed to improve the system’s security and reliability in the case of GPS signal spoofing or jamming. To improve the integration of the microgrid with the utility system, new synchronization and islanding detection algorithms were developed. The developed algorithms overcome the problem of SCADA and PMU based islanding detection methods such as communication failure and frequency stability. In addition, a real-time energy management system with online optimization was developed to manage the energy resources within the microgrid. The security and privacy were also addressed in both the cyber and physical levels. For the physical design, two techniques were developed to address the physical privacy issues by changing the current and electromagnetic signature. For the cyber level, a security mechanism for IEC 61850 GOOSE messages was developed to address the security shortcomings in the standard

Future of asynchronous transfer mode networking

The growth of Asynchronous Transfer Mode (ATM) was considered to be the ideal carrier of the high bandwidth applications like video on demand and multimedia e-learning. ATM emerged commercially in the beginning of the 1990\u27s. It was designed to provide a different quality of service at a speed up 100 Gbps for both real time and non real time application. The turn of the 90\u27s saw a variety of technologies being developed. This project analyzes these technologies, compares them to the Asynchronous Transfer Mode and assesses the future of ATM

Methods and Tools for Battery-free Wireless Networks

Embedding small wireless sensors into the environment allows for monitoring physical processes with high spatio-temporal resolutions. Today, these devices are equipped with a battery to supply them with power. Despite technological advances, the high maintenance cost and environmental impact of batteries prevent the widespread adoption of wireless sensors. Battery-free devices that store energy harvested from light, vibrations, and other ambient sources in a capacitor promise to overcome the drawbacks of (rechargeable) batteries, such as bulkiness, wear-out and toxicity. Because of low energy input and low storage capacity, battery-free devices operate intermittently; they are forced to remain inactive for most of the time charging their capacitor before being able to operate for a short time. While it is known how to deal with intermittency on a single device, the coordination and communication among groups of multiple battery-free devices remain largely unexplored. For the first time, the present thesis addresses this problem by proposing new methods and tools to investigate and overcome several fundamental challenges

Caracterización y optimización térmica de sistemas en chip mediante emulación con FPGAs

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 15/06/2012Tablets and smartphones are some of the many intelligent devices that dominate the consumer electronics market. These systems are complex to design as they must execute multiple applications (e.g.: real-time video processing, 3D games, or wireless communications), while meeting additional design constraints, such as low energy consumption, reduced implementation size and, of course, a short time-to-market. Internally, they rely on Multi-processor Systems on Chip (MPSoCs) as their main processing cores, to meet the tight design constraints: performance, size, power consumption, etc. In a bad design, the high logic density may generate hotspots that compromise the chip reliability. This thesis introduces a FPGA-based emulation framework for easy exploration of SoC design alternatives. It provides fast and accurate estimations of performance, power, temperature, and reliability in one unified flow, to help designers tune their system architecture before going to silicon.El estado del arte, en lo que a diseño de chips para empotrados se refiere, se encuentra dominado por los multi-procesadores en chip, o MPSoCs. Son complejos de diseñar y presentan problemas de disipación de potencia, de temperatura, y de fiabilidad. En este contexto, esta tesis propone una nueva plataforma de emulación para facilitar la exploración del enorme espacio de diseño. La plataforma utiliza una FPGA de propósito general para acelerar la emulación, lo cual le da una ventaja competitiva frente a los simuladores arquitectónicos software, que son mucho más lentos. Los datos obtenidos de la ejecución en la FPGA son enviados a un PC que contiene bibliotecas (modelos) SW para calcular el comportamiento (e.g.: la temperatura, el rendimiento, etc...) que tendría el chip final. La parte experimental está enfocada a dos puntos: por un lado, a verificar que el sistema funciona correctamente y, por otro, a demostrar la utilidad del entorno para realizar exploraciones que muestren los efectos a largo plazo que suceden dentro del chip, como puede ser la evolución de la temperatura, que es un fenómeno lento que normalmente requiere de costosas simulaciones software.Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

ATM network impairment to video quality

Includes bibliographical reference