Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396

Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding

© 2019 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.[EN] This paper presents a low-complexity chase (LCC) decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide an evidence that the proposed method is suitable for RS codes with different rates and Galois fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at the frame error rate that is equal to 10(-6) compared with hard-decision decoding, which is higher than that of an eta = 5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gb/s can be reached in a 90-nm process and 29.1XORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gb/s and requires 5085 LUTs.This work was supported by the Spanish Ministerio de Economia y Competitividad and FEDER under Grant TEC2015-70858-C2-2-R. This paper was recommended by Associate Editor M. Boukadoum.Valls Coquillat, J.; Torres Carot, V.; Canet Subiela, MJ.; García-Herrero, FM. (2019). A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Transactions on Circuits and Systems I Regular Papers. 66(6):2198-2207. https://doi.org/10.1109/TCSI.2018.2882876S2198220766

Error-correction coding for high-density magnetic recording channels.

Finally, a promising algorithm which combines RS decoding algorithm with LDPC decoding algorithm together is investigated, and a reduced-complexity modification has been proposed, which not only improves the decoding performance largely, but also guarantees a good performance in high signal-to-noise ratio (SNR), in which area an error floor is experienced by LDPC codes.The soft-decision RS decoding algorithms and their performance on magnetic recording channels have been researched, and the algorithm implementation and hardware architecture issues have been discussed. Several novel variations of KV algorithm such as soft Chase algorithm, re-encoded Chase algorithm and forward recursive algorithm have been proposed. And the performance of nested codes using RS and LDPC codes as component codes have been investigated for bursty noise magnetic recording channels.Future high density magnetic recoding channels (MRCs) are subject to more noise contamination and intersymbol interference, which make the error-correction codes (ECCs) become more important. Recent research of replacement of current Reed-Solomon (RS)-coded ECC systems with low-density parity-check (LDPC)-coded ECC systems obtains a lot of research attention due to the large decoding gain for LDPC-coded systems with random noise. In this dissertation, systems aim to maintain the RS-coded system using recent proposed soft-decision RS decoding techniques are investigated and the improved performance is presented

A Review :Implementation of Reed Solomon Error Correction & Detec-tion For Wireless Network 802.16

The reed Solomon (255,239) are error-correcting & detecting code. Reed-Solomon codes are the most frequently used digital error control. It is also called as forword error code. The main part of reed-Solomon encoder is the linear feedback shift register that is implemented using VHDL A pipelined RS decoders is proposed of reducing the hardware complexity use the pipelined GFmultiplier in the syndrome computation block, KES block, Forney block, Chien search block and error correction block for provides low com-plexity the extended inversion less Massey-Berlekamp algorithm is used. The extended inversion less Massey-Berlekamp algorithm overcomes both the error locator polynomial and the error evaluator polynomial at the same time

Comparison of code rate and transmit diversity in MIMO systems

A thesis submitted in ful lment of the requirements for the degree of Master of Science in the Centre of Excellence in Telecommunications and Software School of Electrical and Information Engineering, March 2016In order to compare low rate error correcting codes to MIMO schemes with transmit diversity, two systems with the same throughput are compared. A VBLAST MIMO system with (15; 5) Reed-Solomon coding is compared to an Alamouti MIMO system with (15; 10) Reed-Solomon coding. The latter is found to perform signi cantly better, indicating that transmit diversity is a more e ective technique for minimising errors than reducing the code rate. The Guruswami-Sudan/Koetter-Vardy soft decision decoding algorithm was implemented to allow decoding beyond the conventional error correcting bound of RS codes and VBLAST was adapted to provide reliability information. Analysis is also performed to nd the optimal code rate when using various MIMO systems.MT201

Energy-Efficient Digital Signal Processing for Fiber-Optic Communication Systems

Modern fiber-optic communication systems rely on complex digital signal processing (DSP) and forward error correction (FEC), which contribute to a significant amount of the over-all link power dissipation. Bandwidth demands are evergrowing and circuit technology scaling will due to fundamental reasons come to an end; energy-efficient design of DSP is thus necessary both from a sustainability perspective and a technical perspective. This thesis explores energy-efficient design of the sub-systems that are estimated to contribute to the majority of the receiver application-specific integrated-circuit power dissipation: chromatic-dispersion compensation, dynamic equalization, nonlinearity mitigation, and forward error correction. With a focus on real-time-processing circuit implementation of the considered algorithms, aspects such as finite-precision effects, pipelining, and parallel processing are explored, the impact on compensation and correction performance is investigated, and energy-efficient circuit implementations are developed. The sub-systems are investigated both individually, and in a system context. DSP designs showing significant energy-efficiency improvements are presented, as well as very high-throughput, energy-efficient, FEC designs. The subsystems are also considered in the context of datacenter interconnect links, and it is shown that DSP-based coherent systems are feasible even in power constrained settings

The application of forward error correction techniques in wireless ATM

Bibliography: pages 116-121.The possibility of providing wireless access to an ATM network promises nomadic users a communication tool of unparalleled power and flexibility. Unfortunately, the physical realization of a wireless A TM system is fraught with technical difficulties, not the least of which is the problem of supporting a traditional ATM protocol over a non-benign wireless link. The objective of this thesis, titled "The Application of Forward Error Correction Techniques in Wireless ATM' is to examine the feasibility of using forward error correction techniques to improve the perceived channel characteristics to the extent that the channel becomes transparent to the higher layers and allows the use of an unmodified A TM protocol over the channel. In the course of the investigation that this dissertation describes, three possible error control strategies were suggested for implementation in a generic wireless channel. These schemes used a combination of forward error correction coding schemes, automatic repeat request schemes and interleavers to combat the impact of bit errors on the performance of the link. The following error control strategies were considered : 1. A stand alone fixed rate Reed-Solomon encoder/decoder with automatic repeat request. 2. A concatenated Reed-Solomon, convolution encoder/decoder with automatic request and convolution interleaving for the convolution codec. 3. A dynamic rate encoder/decoder using either a concatenated Reed-Solomon, convolution scheme or a Reed-Solomon only scheme with variable length Reed-Solomon words