Design and Simulation of Parallel CRC Generation Architecture for High Speed Application

ABSTRACT: High speed data transmission is the current scenario in networking environment. Cyclic redundancy check (CRC) is essential method for detecting error when the data is transmitted. With challenging the speed of transmitting data, to synchronize with speed, it's necessary to increase speed of CRC generation. Starting from the serial architecture identified a recursive formula from which parallel design is derived. For simulation and functional verification we will use ModelSim and AlteraQuartus 2. A cyclic redundancy check (CRC) is an error detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This paper is based on pipelined CRC method is designed to achieve high throughput by cascading buffers, which improves the time further

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and to enable early stopping of iterations as well. The current state of the art lacks specific CRC implementations for this standard, and most current solutions adopt a fixed degree of parallelism, unsuitable for many turbo decoder architectures. This work proposes a variable parallelism circuit targeting the 3GPP-LTE/LTE-Advanced 24-bit CRC, that can adapt to input data of different sizes. Low complexity is achieved through careful functional sharing among the various parallelisms: comparison with the state of the art shows comparable or superior speed and extremely low complexity

An Optimization Technique for CRC Generation

Abstract: In networking environments, the cyclic redundancy check (CRC) is widely utilized to determine whether errors have been introduced during transmissions over physical links. In this paper, we present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for an arbitrary length of message in parallel. This paper proposes 64 bits parallel CRC architecture based on F matrix with order of generator polynomial is 32 and showed CRC-64 is having less latency and high throughput compared to CRC-32 parallel architecture through Xilinx Simulator

Area efficient parallel lfsr for cyclic redundancy check

Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations

High Speed Low Power Cyclic Redundancy Check-32 using FPGA

Cyclic Redundancy Check (CRC) is a method used for error detection technique and data integrity. CRC take a block of a message‟s bits and divide it by a binary number called polynomial, the result of this division is the checksum that will be added to the message. On the receiver side, the same division will be performed to get the remainder which could be compared with the transmitted checksum if there are no differences that are mean there are no errors. This paper aims to design CRC32 that applied in the Ethernet frame by using Field Programmable Gate Array (FPGA) Virtex-7. Lookup tables and slicing-by-16 algorithm are used together to calculate the CRC32 in parallel. Xilinx ISE used as IDE and synthesis tool and I-Sim used for simulation purposes. The result of this design is 1.250 ns which is the processing time and 102.4 Gbps which is the throughput, furthermore the power consumption is very low as well as the device utilization

High-Performance Hardware and Software Implementations of the Cyclic Redundancy Check Computation

The Cyclic Redundancy Check (CRC) is an error detection code used in many digital transmission and storage systems. The two major research areas surrounding CRCs concern developing computation approaches and studying error detection properties. This thesis aims to explore the various aspects of the CRC computation, with the primary objective being to propose novel computation approaches which outperform the existing ones. The work begins with a thorough examination of the formulations found throughout the literature. Then, their subsequent realizations as hardware architectures and software algorithms are investigated. During this investigation, some improvements are presented including optimizations of the state-space trans­ formed and primitive architectures. Afterward, novel formulations are derived and the most significant contribution consists of a matrix decomposition that gives rise to a high-performance software algorithm. Simulation and implementation results are gathered for both hardware and software deployments of the investigated computa­ tion approaches. The theoretical results obtained by simulations are validated with implementation experiments. The proposed algorithm is shown to outperform the existing comparable low-memory algorithm in terms of time complexity

MorphIC: A 65-nm 738k-Synapse/mm2^2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.Comment: This document is the paper as accepted for publication in the IEEE Transactions on Biomedical Circuits and Systems journal (2019), the fully-edited paper is available at https://ieeexplore.ieee.org/document/876400

Design of a smart power manager for digital communication systems

Portable devices, like mobile phones, are in an increasing need for power due to the growing complexity of applications and services provided by them. At the same time, mobile devices need to adapt their communication techniques so as to be able to work with different communication standards. The need for a multistandard communication circuit arises to overcome such a problem. Unfortunately, these circuits need to consume a considerable amount of power to achieve their designed goal. The researchers use the Dynamic Voltage / Frequency Scheduling technique to reduce power consumption in digital systems. This method employs the task time to schedule the system supply voltage along the task time to reduce the overall consumed power. Since the task time in digital communication systems is not defined, the application of the dynamic voltage/frequency technique on such systems is not possible. In this research, a closer look at the digital circuit power dissipation is given. Then, a new power model is introduced which can predict the digital circuit instantaneous power dissipation accurately. This model is used to build a power control strategy that makes use of the frequency as a control parameter. A setup is carried out using MATLAB to simulate the power of a NOT gate, a multiplexer circuit, a full adder and a two-bit full adder. The results are compared with OrCAD Cadence simulation for the same circuits. The results show that the new model can simulate the power dissipation accurately under different voltages, frequencies, and different technology sizes. In the second part of this research, a smart power manager is designed based on a fuzzy logic controller. The smart power manager makes use of the measured power and the input frequency to produce the required voltage to the digital system. The smart power manager is tested on a multiplexer circuit, two-bit full adder circuit, and cyclic redundancy check circuits. The results of the simulations show that the manager can reduce up to 60% of the consumed power by these circuits in low frequencies and up to 5% of the consumed power in high frequencies. The smart power manager can fulfil the purpose of the dynamic voltage/frequency scheduling technique without the need for the task time. In the final part of this research, the Long Term Evolution (LTE) system is taken as a case study. A unique cyclic redundancy check circuit is designed. This circuit is directed to work with LTE systems, so it has three generators integrated into it. The circuit can select the needed cyclic redundancy generator and produce the required remainder for the LTE system. The smart power manager is modified to supply both the voltage and frequency to the new cyclic redundancy check circuit so that it can control its consumed power. The selection of frequency depends on the used cyclic redundancy generator and the used modulation technique. The selected frequency ensures that the data rate between the LTE stages is constant. The results of the setup show that the smart power manager is capable of reducing the power of the circuit by more than 40% if it was operating at a constant frequency. The smart power manager can lower the power of the cyclic redundancy check circuit by more than 20% if the circuit is running under variable clock frequency. The conclusion driven from the results above proves that the SPM can reduce the consumed power in multi standard systems and Software Defined Radio (SDR) circuits