FPGA Implementation of NPSF Testing Using Block Code Technique

This paper presents a test structure for high speed memories. Built in self test (BIST) give the solution for testing memories and associate hardware for test pattern generation and application for a variety of test algorithms. Memory test algorithm for neighborhood pattern sensitive faults (NPSF) is developed by using block code technique to identify the base cell and deleted neighborhood cells. Test pattern generation can be done by using LFSR and Euler pattern generation. The testing process is verified using Xilinx ISE 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board

Experiments on a three-core cell for high-speed memories

Includes: magnetic memories, external selection, experimental results, memory criteria, design considerations, preliminary design of plane, reference bibliography, and drawings.The coincident-current magnetic-core memory was suggested in 1949 by Jay W. Forrester as a reliable, random-access storage medium. Development of the first working memory of this type, for the Memory Test Computer at M.I.T., established conclusively the superiority of such a memory over competitive systems and paved the way for others to exploit the new device

High-Speed Electronic Memories and Memory Subsystems

Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of high-speed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its implementation in a practical 16-bit memory subsystem

Towards high-speed optical quantum memories

Quantum memories, capable of controllably storing and releasing a photon, are a crucial component for quantum computers and quantum communications. So far, quantum memories have operated with bandwidths that limit data rates to MHz. Here we report the coherent storage and retrieval of sub-nanosecond low intensity light pulses with spectral bandwidths exceeding 1 GHz in cesium vapor. The novel memory interaction takes place via a far off-resonant two-photon transition in which the memory bandwidth is dynamically generated by a strong control field. This allows for an increase in data rates by a factor of almost 1000 compared to existing quantum memories. The memory works with a total efficiency of 15% and its coherence is demonstrated by directly interfering the stored and retrieved pulses. Coherence times in hot atomic vapors are on the order of microsecond - the expected storage time limit for this memory.Comment: 13 pages, 5 figure

Signal processor architecture for backscatter radars

Real time signal processing for backscatter radars which requires computational throughput and I/O rates is discussed. The operations that are usually performed in real time are highly repetitive simple accumulations of samples or of products of samples. The control logic does not depend on the values of the data and general purpose computers are not required for the initial high speed processing. The implications of these facts on the architectures of preprocessors for backscatter radars are explored and applied to the design of the Radar Signal Compender

Virtual lines, a deadlock-free and real-time routing mechanism for ATM networks

In this paper, we present a routing mechanism and buffer allocation mechanism for an ATM switching fabric. Since the fabric will be used to transfer multimedia traffic, it should provide a guaranteed throughput and a bounded latency. We focus on the design of a suitable routing mechanism that is capable of fulfilling these requirements and is free of deadlocks. We will describe two basic concepts that can be used to implement deadlock-free routing. Routing of messages is closely related to buffering. We have organized the buffers into parallel FIFO's, each representing a virtual line. In this way, we not only have solved the problem of head of line blocking, but we can also give real-time guarantees. We will show that for local high-speed networks, it is more advantageous to have a proper flow control than to have large buffers. Although the virtual line concept can have a low buffer utilization, the transfer efficiency can be higher. The virtual line concept allows adaptive routing. The total throughput of the network can be improved by using alternative routes. Adaptive routing is attractive in networks where alternative routes are not much longer than the initial route(s). The network of the switching fabric is built up from switching elements interconnected in a Kautz topology

Virtual lines, a deadlock free and real-time routing mechanism for ATM networks

In this paper we present a routing mechanism and buffer allocation mechanism for an ATM switching fabric. Since the fabric will be used to transfer multimedia traffic it should provide a guaranteed throughput and a bounded latency. We focus on the design of a suitable routing mechanism that is capable to fulfil these requirements and is free of deadlocks. We will describe two basic concepts that can be used to implement deadlock free routing. Routing of messages is closely related to buffering. We have organized the buffers into parallel fifos, each representing a virtual line. In this way we not only have solved the problem of Head Of Line blocking, but we can also give real-time guarantees. We will show that for local high-speed networks it is more advantageous to have a proper flow control than to have large buffers. Although the virtual line concept can have a low buffer utilization, the transfer efficiency can be higher. The virtual lines concept allows adaptive routing. The total throughput of the network can be improved by using alternative routes. Adaptive routing is attractive in networks where alternative routes are not much longer than the initial route(s). The network of the switching fabric is built up from switching elements interconnected in a Kautz topology

High speed lookup table approach to radiometric calibration of multispectral image data

A concept for performing radiometric correction of multispectral image data onboard a spacecraft at very high data rates is presented and demonstrated. This concept utilized a lookup table approach, implemented in hardware, to convert the raw sensor data into the desired corrected output data. The digital lookup table memory was interfaced to a microprocessor to allow the data correction function to be completely programmable. Sensor data was processed with this approach at rates equal to the access time of the lookup table memory. This concept offers flexible high speed data processing for a wide range of applications and will benefit from the continuing improvements in performance of digital memories