ATPG for Dynamic Burn-In Test in Full-Scan Circuits

Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches for stress testing is high temperature burn-in. This work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in tes

Perancangan dan Pembuatan Generator Fluks Radial Tiga Fasa Magnet Permanen Kecepatan Rendah

Based on wind speed data from Meteorology and Geophysics Agency, Indonesia has an average wind speed of about 3-6 m / s. Wind speed can be categorized at low wind speed. So the power station needs a low-speed generator. One solution found from this problem is the development of low speed power plant technology. The wind power plant has an important component of which is a generator which is an electric machine that convert mechanical energy into electrical power. By utilizing a low speed and high torque of the direct drive system of the wind turbine. In designing this low-speed generator the magnetic field is made of neodynium magnets. The generator is designed with a speed of 750 rpm, frequency 50 Hz, induced voltage 15 V and 3 phase. Permanent magnet used with a diameter of 20mm and 3mm thick. The tests included zero load testing, load testing, anchor resistance testing, short-circuit testing and calculating voltage regulation. At the load-bearing load and weightless testing there is a decrease in stress due to the load, where the voltage regulation at the R phase is 16.1%, the S phase is 16.8% and the T phase is 13.2%. The yielded generator voltage phase S is 10.1 Vac, voltage phase R is 10.2 Vac, and then voltage phase T is 10.3 Vac

The Langley 14- by 22-Foot Subsonic Tunnel: Description, Flow Characteristics, and Guide for Users

The Langley 14- by 22-foot Subsonic Tunnel is a closed circuit, single-return atmospheric wind tunnel with a test section that can be operated in a variety of configurations (closed, slotted, partially open, and open). The closed test section configuration is 14.5 ft high by 21.75 ft wide and 50 ft long with a maximum speed of about 338 ft/sec. The open test section configuration has a maximum speed of about 270 ft/sec, and is formed by raising the ceiling and walls, to form a floor-only configuration. The tunnel may be configured with a moving-belt ground plane and a floor boundary-layer removal system at the entrance to the test section for ground effect testing. In addition, the tunnel had a two-component laser velocimeter, a frequency modulated (FM) tape system for dynamic data acquisition, flow visualization equipment, and acoustic testing capabilities. Users of the 14- by 22-foot Subsonic Tunnel are provided with information required for planning of experimental investigations including test hardware and model support systems

Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US

Investigations of detail design issues for the high speed acoustic wind tunnel using a 60th scale model tunnel. Part 2: Tests with the closed circuit

This report summarizes the tests on the 1:60 scale model of the High Speed Acoustic Wind Tunnel (HSAWT) performed during the period June - August 1991. Throughout the testing the tunnel was operated in the 'closed circuit mode,' that is when the airflow was set up by an axial flow fan, which was located inside the tunnel circuit and was directly driven by a motor. The tests were first performed with the closed test section and were subsequently repeated with the open test section, the latter operating with the nozzle-diffuser at its optimum setting. On this subject, reference is made to the report (1) issued January 1991, under contract 17-GFY900125, which summarizes the result obtained with the tunnel operating in the 'open circuit mode.' The tests confirmed the viability of the tunnel design, and the flow distributions in most of the tunnel components were considered acceptable. There were found, however, some locations where the flow distribution requires improvement. This applies to the flow upstream of the fan where the flow was found skewed, thus affecting the flow downstream. As a result of this, the flow appeared separated at the end of the large diffuser at the outer side. All tests were performed at NASA LaRC

Calibration of the 13- by 13-inch adaptive wall test section for the Langley 0.3-meter transonic cryogenic tunnel

A 13 by 13 inch adaptive wall test section was installed in the 0.3 Meter Transonic Cryogenic Tunnel circuit. This new test section is configured for 2-D airfoil testing. It has four solid walls. The top and bottom walls are flexible and movable whereas the sidewalls are rigid and fixed. The wall adaptation strategy employed requires the test section wall shapes associated with uniform test section Mach number distributions. Calibration tests with the test section empty were conducted with the top and bottom walls linearly diverged to approach a uniform Mach number distribution. Pressure distributions were measured in the contraction cone, the test section, and the high speed diffuser at Mach numbers from 0.20 to 0.95 and Reynolds numbers from 10 to 100 x 10 (exp 6)/per foot

A very high density floating electrode flexible sensor array for high-resolution measurements of contact forces

pre-printWe present the development, fabrication and testing results of a new high-density flexible sensor array (HDFA) suitable of recording three-axis stresses with high spatial resolution. The new HDFA consists of 676 (26×26) sensing cells fabricated on top of a high-density flex circuit substrate. Each sensing cell is implemented using four floating comb electrodes separated from the flex substrate by a thin layer of a compressible PDMS film. Each sensing cell measures 2.77×2.55 mm2 thus packing 2704 capacitors in an area of ~ 50 cm2. The HDFA is read using a high-speed switched-capacitor circuit with a 13-bit resolution at full frame rates of 100 Hz (~0.8Mb/s). The new array is capable of detecting contact line displacements as low as 35 μm and contact line velocities as low as 38 μm/s

High-freequency CMOS VLSI chip testability and on-chip interconnect modeling

As high-speed digital and radio-frequency mixed-signal integrated circuits become increasingly common in product designs in industry, it is important for VLSI designers to be familiar with the challenges of chip testing and the behavior of circuit elements, including on-chip interconnect, at high frequencies. Expensive, specialized test equipment and software simulation packages for high-frequency chip testing and design are not always accessible for student research. This thesis documents the setup and characterization of a best-possible environment for high-frequency chip testing and data acquisition using existing laboratory equipment and resources. Experimental methodologies and measurement results of on-chip interconnect signal integrity and delay, ring oscillator noise and timing jitter, and time-domain reflectometry (TDR) testing are presented. Methods of modeling on-chip interconnect at high frequencies using field solvers and equivalent circuits are discussed. Lastly, the designs of single-ended and differential ring oscillators, for use in future voltage-controlled oscillator (VCO) and phase-locked loop (PLL) test chip designs, are presented and analyzed