Fault-tolerant interconnection networks for multiprocessor systems

Interconnection networks represent the backbone of multiprocessor systems. A failure in the network, therefore, could seriously degrade the system performance. For this reason, fault tolerance has been regarded as a major consideration in interconnection network design. This thesis presents two novel techniques to provide fault tolerance capabilities to three major networks: the Baseline network, the Benes network and the Clos network. First, the Simple Fault Tolerance Technique (SFT) is presented. The SFT technique is in fact the result of merging two widely known interconnection mechanisms: a normal interconnection network and a shared bus. This technique is most suitable for networks with small switches, such as the Baseline network and the Benes network. For the Clos network, whose switches may be large for the SFT, another technique is developed to produce the Fault-Tolerant Clos (FTC) network. In the FTC, one switch is added to each stage. The two techniques are described and thoroughly analyzed

Reduce the Cross Talk in Omega Network by Using Windowing Techniques

When we work on a distributed network with n number of systems attached with m number of resources. In such case there are number of approaches to connect the system and the resources. One of such approach is Multistage networks. Where some middle level interface systems or the switches are attached between the systems and the resources. But such kind of networks having the problem of confliction when more than one transmission is taken place at one time. In such case there is the possibility that any one line can share more than one transmissions. As the conflictions occur there are much chances of data loss over the network. We are providing the solution for the above defined problem in case of Omega Networks. In this paper we proposed solution the system will first detect the confliction using windowing method. Once the confliction detected the next step is to vary the time of transmission between these two transmissions. As the communication is performed at different time lines it will resolve the problem of confliction in omega networks

Removal of Cross Talk in Omega Switch Network by Using Improve Windowing Technique

An optical computer network is a network that relies primarily on the computing power and bandwidth of the participants in the network rather than concentrating it in a relatively low number of servers. Such networks are useful for many purposes. Sharing content files (see file sharing) containing audio, video, data or anything in digital format is very common, and real time data, such as telephony traffic, is also passed using Optical technology. The proposed work is about to handle the network fault in case of cross talk in a switched network. In this work we are presenting the complete work with Omega Network. The work includes the analysis of existing methodologies to detect the confliction in cross talk. As the confliction is detected the next work is perform the talk with a smaller delay such that it will avoid the cross talk over the networ

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Blocking performance of extended pruned vertically stacked optical banyan structure under different link failure conditions

The blocking performance of extended pruned vertically stacked optical banyan (VSOB) networks under different link failure conditions has been analyzed in this paper. We applied plane fixed routing with linear search and plane fixed routing with random search algorithms to route the optical data through the network in our simulation. Our simulation results show that adding one or two extra planes to the pruned VSOB network reduces the blocking probability significantly. Beyond two extra planes, the decrease of blocking probability is not so significant. A close approximation of the minimum number of planes required to make the extended pruned vertically stacked optical banyan networks nonblocking has been presented

An O(n) time discrete relaxation architecture for real-time processing of the consistent labeling problem

technical reportDiscrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from 0(n2m3 ) time complexity and Oinhn2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly configurable DRA3 architecture