1,949 research outputs found
Using Short Synchronous WOM Codes to Make WOM Codes Decodable
In the framework of write-once memory (WOM) codes, it is important to
distinguish between codes that can be decoded directly and those that require
that the decoder knows the current generation to successfully decode the state
of the memory. A widely used approach to construct WOM codes is to design first
nondecodable codes that approach the boundaries of the capacity region, and
then make them decodable by appending additional cells that store the current
generation, at an expense of a rate loss. In this paper, we propose an
alternative method to make nondecodable WOM codes decodable by appending cells
that also store some additional data. The key idea is to append to the original
(nondecodable) code a short synchronous WOM code and write generations of the
original code and of the synchronous code simultaneously. We consider both the
binary and the nonbinary case. Furthermore, we propose a construction of
synchronous WOM codes, which are then used to make nondecodable codes
decodable. For short-to-moderate block lengths, the proposed method
significantly reduces the rate loss as compared to the standard method.Comment: To appear in IEEE Transactions on Communications. The material in
this paper was presented in part at the 2012 IEEE International Symposium on
Information Theory, Cambridge, MA, July 201
When Do WOM Codes Improve the Erasure Factor in Flash Memories?
Flash memory is a write-once medium in which reprogramming cells requires
first erasing the block that contains them. The lifetime of the flash is a
function of the number of block erasures and can be as small as several
thousands. To reduce the number of block erasures, pages, which are the
smallest write unit, are rewritten out-of-place in the memory. A Write-once
memory (WOM) code is a coding scheme which enables to write multiple times to
the block before an erasure. However, these codes come with significant rate
loss. For example, the rate for writing twice (with the same rate) is at most
0.77.
In this paper, we study WOM codes and their tradeoff between rate loss and
reduction in the number of block erasures, when pages are written uniformly at
random. First, we introduce a new measure, called erasure factor, that reflects
both the number of block erasures and the amount of data that can be written on
each block. A key point in our analysis is that this tradeoff depends upon the
specific implementation of WOM codes in the memory. We consider two systems
that use WOM codes; a conventional scheme that was commonly used, and a new
recent design that preserves the overall storage capacity. While the first
system can improve the erasure factor only when the storage rate is at most
0.6442, we show that the second scheme always improves this figure of merit.Comment: to be presented at ISIT 201
Time-Space Constrained Codes for Phase-Change Memories
Phase-change memory (PCM) is a promising non-volatile solid-state memory
technology. A PCM cell stores data by using its amorphous and crystalline
states. The cell changes between these two states using high temperature.
However, since the cells are sensitive to high temperature, it is important,
when programming cells, to balance the heat both in time and space.
In this paper, we study the time-space constraint for PCM, which was
originally proposed by Jiang et al. A code is called an
\emph{-constrained code} if for any consecutive
rewrites and for any segment of contiguous cells, the total rewrite
cost of the cells over those rewrites is at most . Here,
the cells are binary and the rewrite cost is defined to be the Hamming distance
between the current and next memory states. First, we show a general upper
bound on the achievable rate of these codes which extends the results of Jiang
et al. Then, we generalize their construction for -constrained codes and show another construction for -constrained codes. Finally, we show that these two
constructions can be used to construct codes for all values of ,
, and
플래시 메모리를 위한 양방향 비대칭 오류 정정 부호 및 간섭 완화 기법
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 이정우.Recently, NAND multi-level cell (MLC) flash memories are now widely used due to low cost and high capacity. However, when the number of cell levels increases, cell-to-cell interference (C2CI) which shifts threshold voltage may degrades the error rate in reading process. There are several approaches to alleviate the errors caused by the threshold voltage shift and we discuss error correcting codes and message encoding schemes.
First, we propose error correcting codes that are effective for multi-level cell flash memory and non-binary WOM (write once memory) codes. In particular, we focus on bidirectional error correction codes. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. The code treats both upward and downward errors when the error magnitude in each direction differs. The maximum magnitudes of the upward error and downward error are lu and ld, respectively. One of proposed codes extends the technique of the distinct sum sets to the bidirectional error correction codes. The other code is bidirectional limited magnitude error correction codes based on modulo operation and uses non-binary conventional error correction codes. These proposed codes can reduce the parity size, and have better error correction performance than the conventional error correction codes when the code rate is equal. Furthermore, error correcting schemes for non-binary WOM codes are discussed. WOM codes is a coding scheme that allows information to be written in a memory cell multiple times without erasure, and conventional error correction codes cannot be directly applied to WOM codes. The advantages of the proposed methods are that these are practical and systematic codes, and the complexity of encoding and decoding processes are low. We also introduce effective error locating limited-magnitude parity check error correction codes for the MLC flash memory error with lower complexity.
Second, we introduce coding schemes to lower the generated interferences by cell to cell interference. It is known that C2CI is caused by the threshold voltage change of neighbor cells in writing operation. The amount of threshold voltage change is proportional to the magnitude. To minimize the generated interference, the average magnitude needs to be decreased. We propose two new C2CI reduction coding schemes that adjust the average magnitude to reduce C2CI. The proposed coding scheme deals with q-ary message codes, and generates fixed length codes. Message codewords are divided into several blocks, and are modified by modulo addition with proper values to minimize the average magnitude. We also propose low energy Huffman codes based on entropy coding when the frequency of symbols is not distributed uniformly. This scheme produces variable-length codes without redundancy. We modified Huffman codes to minimize average number of high bits ('1' bits). We show that proposed codes generate optimal codewords which have minimum high bits with minimum average codeword length.Chapter 1 Introduction 1
1.1 Backgrounds 1
1.2 Scope and Organization 5
Chapter 2 MLC Flash Memory Interference and Mitigation Techniques for Reliability 9
2.1 MLC flash memory and interference 9
2.2 Signal processing based interference mitigation in MLC flash memories 15
2.3 WOM codes 22
2.4 Asymmetric limited-magitude error correction codes based on distinct sum set 27
Chapter 3 Error Correction Codes for Flash Memories 29
3.1 Introduction 29
3.2 Bidirectional error correction codes for non-binary WOM codes based on distinct sum sets 30
3.2.1 Bidirectional error correction codes based on distinct sum sets 30
3.2.2 Error correction coding schemes for WOM codes based on distinct sum sets 41
3.3 Bidirectional error correction codes for WOM codes based on modulo operation 44
3.3.1 Bidirectional error correction codes based on modulo operation 44
3.3.2 Performance simulation of bidirectional error correction codes based on modulo operation 54
3.3.3 Error correction coding schemes for WOM codes based on modulo operation 58
3.4 Performance of error correction coding schemes for WOM code 61
3.5 Error locating parity check codes for errors with limited magnitude 68
3.6 Summary 77
Chapter 4 On Interference Mitigating Codes for Multi-level Flash Memories 79
4.1 Introduction 79
4.2 The modeling of generated interference in flash memory 80
4.3 Coding schemes for interference mitigation 83
4.3.1 Minimum energy coding 83
4.3.2 Module shift coding 85
4.3.3 Low energy Huffman code 89
4.4 Performance analysis of proposed coding schemes 91
4.4.1 Performance analysis of ME codes 91
4.4.2 Performance analysis of MS codes 93
4.4.3 Performance of low-energy Huffman codes 97
4.4.4 C2CI reduction performance 99
4.5 Summary 102
Chapter 5 Conclusions 105
Appendix A 109
A.1 Performance analysis of MS coding with eta=2 case in chap. 4.4.2. 109
Bibliography 113
Abstract in Korean 120Docto
Trade-offs between Instantaneous and Total Capacity in Multi-Cell Flash Memories
The limited endurance of flash memories is a major
design concern for enterprise storage systems. We propose a
method to increase it by using relative (as opposed to fixed)
cell levels and by representing the information with Write
Asymmetric Memory (WAM) codes. Overall, our new method
enables faster writes, improved reliability as well as improved
endurance by allowing multiple writes between block erasures.
We study the capacity of the new WAM codes with relative levels,
where the information is represented by multiset permutations
induced by the charge levels, and show that it achieves the
capacity of any other WAM codes with the same number of
writes. Specifically, we prove that it has the potential to double
the total capacity of the memory. Since capacity can be achieved
only with cells that have a large number of levels, we propose a
new architecture that consists of multi-cells - each an aggregation
of a number of floating gate transistors
Algorithms and Data Representations for Emerging Non-Volatile Memories
The evolution of data storage technologies has been extraordinary. Hard disk drives
that fit in current personal computers have the capacity that requires tons of transistors
to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory
(NVM). NVMs provide excellent performance such as random access, high I/O speed, low
power consumption, and so on. The storage density of NVMs keeps increasing following
Moore’s law. However, higher storage density also brings significant data reliability issues.
When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer
to each other, and noise in the devices will become no longer negligible. Consequently,
data will be more prone to errors and devices will have much shorter longevity.
This dissertation focuses on mitigating the reliability and the endurance issues for two
major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main
research tools include a set of coding techniques for the communication channels implied
by flash memory and PCM. To approach the problems, at bit level we design error
correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint
coding scheme for endurance and reliability, error scrubbing methods for controlling storage
channel quality, and study codes that are inherently resisting to typical errors in flash
and PCM; at higher levels, we are interested in analyzing the structures and the meanings
of the stored data, and propose methods that pass such metadata to help further improve
the coding performance at bit level. The highlights of this dissertation include the first
set of write-once memory code constructions which correct a significant number of errors,
a practical framework which corrects errors utilizing the redundancies in texts, the first
report of the performance of polar codes for flash memories, and the emulation of rank
modulation codes in NAND flash chips
Signal Processing for Caching Networks and Non-volatile Memories
The recent information explosion has created a pressing need for faster and more reliable data storage and transmission schemes. This thesis focuses on two systems: caching networks and non-volatile storage systems. It proposes network protocols to improve the efficiency of information delivery and signal processing schemes to reduce errors at the physical layer as well. This thesis first investigates caching and delivery strategies for content delivery networks. Caching has been investigated as a useful technique to reduce the network burden by prefetching some contents during o˙-peak hours. Coded caching [1] proposed by Maddah-Ali and Niesen is the foundation of our algorithms and it has been shown to be a useful technique which can reduce peak traffic rates by encoding transmissions so that different users can extract different information from the same packet. Content delivery networks store information distributed across multiple servers, so as to balance the load and avoid unrecoverable losses in case of node or disk failures. On one hand, distributed storage limits the capability of combining content from different servers into a single message, causing performance losses in coded caching schemes. But, on the other hand, the inherent redundancy existing in distributed storage systems can be used to improve the performance of those schemes through parallelism. This thesis proposes a scheme combining distributed storage of the content in multiple servers and an efficient coded caching algorithm for delivery to the users. This scheme is shown to reduce the peak transmission rate below that of state-of-the-art algorithms
Towards Endurable, Reliable and Secure Flash Memories-a Coding Theory Application
Storage systems are experiencing a historical paradigm shift from hard disk to nonvolatile memories due to its advantages such as higher density, smaller size and non-volatility. On the other hand, Solid Storage Disk (SSD) also poses critical challenges to application and system designers. The first challenge is called endurance. Endurance means flash memory can only experience a limited number of program/erase cycles, and after that the cell quality degradation can no longer be accommodated by the memory system fault tolerance capacity. The second challenge is called reliability, which means flash cells are sensitive to various noise and disturbs, i.e., data may change unintentionally after experiencing noise/disturbs. The third challenge is called security, which means it is impossible or costly to delete files from flash memory securely without leaking information to possible eavesdroppers.
In this dissertation, we first study noise modeling and capacity analysis for NAND flash memories (which is the most popular flash memory in market), which gains us some insight on how flash memories are working and their unique noise. Second, based on the characteristics of content-replication codewords in flash memories, we propose a joint decoder to enhance the flash memory reliability. Third, we explore data representation schemes in flash memories and optimal rewriting code constructions in order to solve the endurance problem. Fourth, in order to make our rewriting code more practical, we study noisy write-efficient memories and Write-Once Memory (WOM) codes against inter-cell interference in NAND memories. Finally, motivated by the secure deletion problem in flash memories, we study coding schemes to solve both the endurance and the security issues in flash memories. This work presents a series of information theory and coding theory research studies on the aforesaid three critical issues, and shows that how coding theory can be utilized to address these challenges
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