AlGaN/GaN 전력소자의 특성 향상을 위한 식각과 절연막에 관한 연구

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 서광석.최근 에너지 위기와 환경규제 강화, 친환경 녹색성장 등의 이슈가 대두되어 에너지 절감과 환경 보호 분야에 IT 기술을 접목, 활용하는 그린 IT 패러다임이 부각되고 있다. 현재 고유가 환경규제 강화에 대응하기 위해 하이브리드 자동차, 전기자동차 등 친환경 미래형 자동차 개발이 요구되고 있으며, 자동차에서 전장부품이 차지하는 원가비중은 약 40%까지 달할 것으로 전망되고 이 중 반도체가 차지하는 비용은 약 30% 정도로 추정된다. 이러한 자동차 전장부품에서 전력소자가 핵심부품으로 자리 잡을 전망이다. 지금까지는 실리콘 기반의 전력소자 기술이 전력반도체 시장의 대부분을 주도하고 있지만 전력기기 로드맵에 의하면 전력밀도가 해를 거듭하면서 지속적으로 증가하기 때문에 내열, 내압, 전력손실, 전력밀도 등에서 나타나는 많은 한계를 가지고 있는 현재의 실리콘 기반 전력시스템은 효율이 눈에 띄게 감소할 것이 자명하므로 전력시스템의 전력전송효율과 신뢰성의 중요성이 크게 대두되고 있다. 이 같은 사회적 요구로 볼 때 현재의 실리콘 전력소자의 기술적 한계를 뛰어넘는 고효율의 차세대 전력반도체 소자의 개발이 시급히 요구되며 SiC와 GaN와 같은 광대역 반도체가 차세대 전력반도체 소재로 유력해지고 있다. 또한 전력시스템에서는 시스템의 안전성과 회로의 간략화를 위하여 normally-off (증강형) 전력소자가 요구되기 때문에 normally-off (증강형) GaN 전력소자에 대한 개발이 필수적이다. 본 그룹에서는 gate-recess 공정을 이용하여 normally-off 동작을 실현하는 연구를 진행하였고, gate-recess 시 발생하는 식각 데미지를 줄이고 우수한 성능의 게이트 절연막을 개발하여 GaN 전력 반도체 소자의 전기적 특성 및 신뢰성을 개선하는 연구를 진행하였다. 식각 연구에서는 최종적으로 셀프 DC 바이어스가 낮은 O2, BCl3 플라즈마를 이용한 atomic layer etching을 개발하였고, 이를 통해 거칠기가 작고 표면 N vacancy가 적은 고품질의 (Al)GaN 표면을 얻을 수 있었다. 박막 연구에서는 Oxide 박막 증착 시, (Al)GaN 표면에 생성되어 계면 특성을 악화시키는 Ga2O3 생성을 막기위해 ALD AlN layer를 개발 및 적용하여 박막/(Al)GaN 계면 특성을 향상시켰다. 이로 인해 소자의 동작전류 증가 및 Dit 감소 결과를 얻을 수 있었고 스트레스에 따른 문턱전압 이동 특성의 감소로 소자의 신뢰성 또한 개선시킬 수 있었다. 이는 타 기관의 결과와 비교해도 뒤떨어지지 않는 우수한 특성을 보여주었다. 결론적으로 본 연구의 작은 플라즈마 데미지를 갖는 식각공정과 고품질 절연막 개발을 통해 우수한 특성의 GaN 전력소자를 구현할 수 있었고 향후 차세대 전력소자에 적용을 위한 가능성을 확보하였다.The Si technology for power devices have already approached its theoretical limitations due to its physical and material properties, despite the considerable efforts such as super junction MOSFET, trench gate, and insulated gate bipolar transistors. To overcome these limitations, many kinds of compound materials such as GaN, GaAs, SiC, Diamond and InP which have larger breakdown voltage and high electron velocity than Si also have been studied as future power devices. GaN has been considered as a breakthrough in power applications due to its high critical electric field, high saturation velocity and high electron mobility compared to Si, GaAs, and SiC. Especially, AlGaN/GaN heterostructure field-effect transistors (HFETs) have been considered as promising candidates for high power and high voltage applications. However, these AlGaN/GaN heterostructure field-effect transistors with the 2DEG are naturally normally-on, which makes the devices difficult to deplete the channel at zero gate bias. Among the various methods for normally-off operation of GaN devices, gate-recess method is a promising method because it can be easier to implement than other approaches and ensure normally-off operation. However, charge trapping at the interface between gate dielectric and (Al)GaN and in the gate dielectric is a big issue for recessed gate MIS-HEMTs. This problem leads to degradation of channel mobility, on-resistance and on-current of the devices. Especially, Vth hysteresis after a positive gate voltage sweep and Vth shift under a gate bias stress are important reliability challenges in gate recessed MIS-HEMTs. The scope of this work is mainly oriented to achieve high quality interface at dielectric/(Al)GaN MIS by studying low damage etching methods and the ALD process of various dielectric layers. In the etching study, various etching methods for normally-off operation have been studied. Also, etching damage was evaluated by various methods such as atomic force microscopy (AFM), photoluminescence (PL) measurements, X-ray photoelectron spectroscopy (XPS) measurements and electrical properties of the recessed schottky devices. Among the etching methods, the ALE shows the smoothest etched surface, the highest PL intensity and N/(Al+Ga) ratio of the etched AlGaN surface and the lowest leakage current of the gate recessed schottky devices. It is suggested that the ALE is a promising etching technique for normally-off gate recessed AlGaN/GaN MIS-FETs. In the study of dielectrics, excellent electrical characteristics and small threshold volt¬age drift under positive gate bias stress are achieved by employing the SiON interfacial layer. However, considerable threshold voltage drift is observed under the higher positive gate bias stress even at the devices using the SiON interfacial layer. For further improvement of interface and reliability of devices, we develop and optimize an ALD AlN as an interfacial layer to avoid the formation of poor-quality oxide at the dielectric/(Al)GaN interface. We also develop an ALD AlHfON as a bulk layer, which have a high dielectric constant and low leakage current and high breakdown field characteristics. Devices with AlN/AlON/AlHfON layer show smaller I-V hysteresis of ~10 mV than that of devices with AlON/AlHfON layer. The extracted static Ron values of devices with AlN/AlON/AlHfON and AlON/AlHfON are 1.35 and 1.69 mΩ·cm2, respectively. Besides, the effective mobility, Dit and threshold voltage instability characteristics are all improved by employing the ALD AlN. In conclusion, for high performance and improvement of reliability of normally-off AlGaN/GaN MIS-FETs, this thesis presents an etching technique for low damage etching and high-quality gate dielectric layer and suggests that the ALE and ALD AlN/AlON/AlHfON gate dielectric are very promising for the future normally-off AlGaN/GaN MIS-FETsChapter 1. Introduction 1 1.1. Backgrounds 1 1.2. Normally-off Operation in AlGaN/GaN HFETs 3 1.3. Issues and Feasible Strategies in AlGaN/GaN MIS-HFETs 11 1.4. Research Aims 15 1.5. References 17 Chapter 2. Development and Evaluation of Low Damage Etching processes 22 2.1. Introduction 22 2.2. Various Evaluation Methods of Etching Damage 24 2.3. Low-Damage Dry Etching Methods 29 2.3.1. Inductively Coupled Plasma-Reactive Ion Etching Using BCl3/Cl2 Gas Mixture 29 2.3.2. Digital Etching Using Plasma Asher and HCl 34 2.3.3. Atomic Layer Etching Using Inductively Coupled Plasma–Reactive Ion Etching System (ICP-RIE) 50 2.4. Conclusion 75 2.5. References 76 Chapter 3. SiON/HfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 80 3.1. Introduction 80 3.2. ALD Processes for SiON and HfON 83 3.3. Electrical Characteristics of ALD SiON, HfON and SiON/HfON Dual Layer on n-GaN 87 3.4. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with SiON/HfON Dual Layer 95 3.5. Conclusion 113 3.6. References 114 Chapter 4. High Quality AlN/AlON/AlHfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 120 4.1. Introduction 120 4.2. Development of ALD AlN/AlON/AlHfON Gate Stack 122 4.2.1. Process Optimization for ALD AlN 122 4.2.2. ALD AlN as an Interfacial Layer 144 4.2.3. Thickness Optimization of AlN/AlON/ AlHfON Layer 149 4.2.4. ALD AlHfON Optimization 159 4.2.5. Material Characteristics of AlN/AlON/AlHfON Layer 167 4.3. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with AlN/AlON/AlHfON Layer 171 4.4. Conclusion 182 4.5. References 183 Chapter 5. Concluding Remarks 188 Appendix. 190 A. N2 Plasma Treatment Before Dielectric Deposition 190 B. Tri-gate Normally-on/off AlGaN/GaN MIS-FETs 200 C. AlGaN/GaN Diode with MIS-gated Hybrid Anode and Edge termination 214 Abstract in Korean 219 Research Achievements 221Docto

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