CMOL: Second Life for Silicon?

This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the "bottom-up" approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 1012 cm2 and that they may provide an unparalleled information processing performance, up to 1020 operations per cm2 per second, at manageable power consumption.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

An ultra low-power hardware accelerator for automatic speech recognition

Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems, while delivering high-performance. In this paper, we present an accelerator for large-vocabulary, speaker-independent, continuous speech recognition. It focuses on the Viterbi search algorithm, that represents the main bottleneck in an ASR system. The proposed design includes innovative techniques to improve the memory subsystem, since memory is identified as the main bottleneck for performance and power in the design of these accelerators. We propose a prefetching scheme tailored to the needs of an ASR system that hides main memory latency for a large fraction of the memory accesses with a negligible impact on area. In addition, we introduce a novel bandwidth saving technique that removes 20% of the off-chip memory accesses issued during the Viterbi search. The proposed design outperforms software implementations running on the CPU by orders of magnitude and achieves 1.7x speedup over a highly optimized CUDA implementation running on a high-end Geforce GTX 980 GPU, while reducing by two orders of magnitude (287x) the energy required to convert the speech into text.Peer ReviewedPostprint (author's final draft

Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti

A low-power, high-performance speech recognition accelerator

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at high energy cost, not being affordable for the tiny power-budgeted mobile devices. Hardware acceleration reduces energy-consumption of ASR systems, while delivering high-performance. In this paper, we present an accelerator for largevocabulary, speaker-independent, continuous speech-recognition. It focuses on the Viterbi search algorithm representing the main bottleneck in an ASR system. The proposed design consists of innovative techniques to improve the memory subsystem, since memory is the main bottleneck for performance and power in these accelerators' design. It includes a prefetching scheme tailored to the needs of ASR systems that hides main memory latency for a large fraction of the memory accesses, negligibly impacting area. Additionally, we introduce a novel bandwidth-saving technique that removes off-chip memory accesses by 20 percent. Finally, we present a power saving technique that significantly reduces the leakage power of the accelerators scratchpad memories, providing between 8.5 and 29.2 percent reduction in entire power dissipation. Overall, the proposed design outperforms implementations running on the CPU by orders of magnitude, and achieves speedups between 1.7x and 5.9x for different speech decoders over a highly optimized CUDA implementation running on Geforce-GTX-980 GPU, while reducing the energy by 123-454x.Peer ReviewedPostprint (author's final draft

Thermo-Electric Generator Evaluation Board

Thermoelectric generators (TEGs) are solid-state devices that convert temperature gradients into electrical energy. TEGs are desirable sources of energy as they require low maintenance and have high reliability with potential for use in low power and remote applications. To date, no simple and affordable, common test platform for evaluating the performance of TEGs in their associated environment exists. This project is aimed at providing such a platform to deliver performance data that is crucial in power budgeting and viability studies of TEG-powered applications. The design utilizes the common LTC3109 converter chip and an off-the-shelf micro-controller for temperature and load current measurements. The setup automatically regulates the electronic load to achieve maximum power transfer and measurement data can either be observed in real-time through a USB-serial host communication port or logged at a user adjustable rate

Millimeter wave wireless system based on point to multipoint transmissions

The continuously growing traffic demand has motivated the exploration of underutilized millimeter wave frequency spectrum for future mobile broadband communication networks. Research activities focus mainly on the use of the V-band (59 - 64 GHz) and E-band (71 - 76 & 81 - 84 GHz) to offer multi-gigabit point to point transmissions. This paper describes an innovative W-band (92-95 GHz) point to multipoint wireless network for high capacity access and backhaul applications. Point to multipoint wireless networks suffer from limited RF power available. The proposed network is based on a high power, wide band traveling wave tube of new generation and an affordable high performance transceiver. These new devices enable a new transmission paradigm and overcome the relevant technological challenges imposed by the high atmosphere attenuation and the presently lack of power amplification required to provide adequate coverage at millimeter waves

Design of Audio Player and Recorder on STM 32F4 Discovery Board

With the advancement in semiconductor technology, scope for development of embedded systems has increased manifolds. New processors with improved computing capabilities and low power consumption have further accelerated the developments in embedded domain. Consumers are looking for affordable multimedia devices with high performance and durability making embedded developers to think creatively and use all resources at hand to meet the desired user specifications. This is one such attempt by designing an Audio Player and Recorder to play the wave audio files from a USB flash drive and recording the audio in USB flash drive in the same format. In this application MEMS microphone is used for recording the audio dat