High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

© Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

A robust high-efficiency cross-coupled charge pump circuit without blocking transistors

This document is the Accepted Manuscript version of the following article: Minglin Ma, Xinglong Cai, Yichuang Sun, and Nike George, ‘A robust high-efficiency cross-coupled charge pump circuit without blocking transistors’, Analog Integrated Circuits and Signal Processing, Vol. 95 (3): 395-401, June 2018. Under embargo until 16 March 2019. The final publication is available at Springer via: https://doi.org/10.1007/s10470-018-1149-xA fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.Peer reviewe

A High Efficiency and Low Ripple Cross-Coupled Charge Pump Circuit

A fully integrated cross-coupled charge pump circuit with four-clock signals and a new method of body bias have been proposed. The new clock scheme eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the supply voltage. We have also solved the gate-oxide overstress problem in the conventional charge pump circuits and enhanced the reliability. The proposed charge pump circuit has been simulated using Spectre and in the TSMC 0.18um CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5V is 99.8%. Moreover, the output ripple voltage has been significantly reduced.Peer reviewe

High-efficiency high voltage hybrid charge pump design with an improved chip area

A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage

Analysis and design of switched-capacitor DC-DC converters with discrete event models

Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power integrated systems. The analysis and design processes of an SCDDC impact the performance and power efficiency of the whole system. Conventionally, researchers carry out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue attributes of an SCDDC, such as the charge flow current or the equivalent output impedance, have been studied in considerable detail for performance enhancement. However, in most existing work, less attention is paid to the analysis of discrete events (e.g. digital signal transitions) and the relationships between discrete events in SCDDCs. These discrete events and the relationships between discrete events also affect the performance of SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by unhealthy discrete states. For example, MOS devices in an SCDDC could conduct undesirably under certain combinations of signals, resulting in reversion losses (a type of leakage in SCDDCs). However, existing work only use verbal reasoning and waveform descriptions when studying these discrete events, which may cause confusion and result in an informal design process consisting of intuitive design and backed up merely by validation based on natural language discussions and simulations. There is therefore a need for formalised methods to describe and analyse these discrete events which may facilitate systematic design techniques. This thesis presents a new method of analysing and designing SCDDCs using discrete event models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are commonly used in asynchronous circuits to formally describe and analyse the relationships between discrete transitions. Modelling SCDDCs with discrete event models provides a formal way to describe the relations between discrete transitions in SCDDCs. These discrete event models can be used for analysis, verification and even design guidance for SCDDC design. The rich set of existing analysis methods and tools for discrete event models could be applied to SCDDCs, potentially improving the analysis and design flow for them. Moreover, since Petri nets and STGs are generally used to analyse and design asynchronous circuits, modelling and designing SCDDCs with STG models may additionally facilitate the incorporation of positive features of asynchronous circuits in SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong), which avoids the potential confusion due to natural language and waveform descriptions. Then the concurrency and causality relations described in SC-STG model are extended to Petri nets, with which the presence of reversion losses can be formally determined and verified. Finally, based on the STG and Petri net models, a new design method for reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method, reversion losses are entirely removed by introducing asynchronous controls, synthesised with the help of a software synthesis toolkit “Workcraft”. To demonstrate the analysis capabilities of the method, several cross-coupled voltage doublers (a type of SCDDC) are analysed and studied with discrete event models as examples in this thesis. To demonstrate the design capabilities of the method, a new reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage doubler is widely used in low power integrated systems such as flash memories, LCD drivers and wireless energy harvesting systems. The proposed modelling method is potentially used in both research and industrial area of those applications for a formal and high-efficiency design proces

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

A Charge Pump Architecture with High Power-Efficiency and Low Output Ripple Noise in 0.5 μm CMOS Process Technology

The demand of portable consumer electronic devices is skyrocketing day-by-day. Such modern integrated microsystems have several functional blocks which require different voltages to operate adequately. DC-DC converter circuits are used to generate different voltage domains for different functional blocks on large integrated microsystems from a single voltage battery-operated power supply. Charge pump is an inductorless DC-DC converter which generates higher positive voltage or lower voltage or negative voltage from the applied reference voltage. A charge pump circuit uses switches for charge transfer action and capacitors for charge storage. The thesis presents a high power-efficiency charge pump architecture with low output ripple noise in the AMI N-well 0.5 µm CMOS process technology. The switching action of the proposed charge pump architecture is controlled by a dual phase non-overlapping clock system. In order to achieve high power-efficiency, the power losses due to the leakage currents, the finite switch resistance and the imperfect charge transfer between the capacitors are taken into consideration and are minimized by proper switching of the charge transfer switches and by using different auxiliary circuits. To achieve low output ripple noise, the continuous current pumping method is proposed and implemented in the charge pump architecture. The proposed charge pump can operate over the wide input voltage range varying from 3 V to 7 V with the power conversion efficiency of 90%. The loading current drive capability of the proposed charge pump is ranging from 0 to 45 mA. The worst case output ripple voltage is less than 25 mV. To prove the concept, the design of the proposed charge pump is simulated rigorously over different process, temperature and voltage corners

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Energy-Efficient Start-Up Dickson Charge Pump for Batteryless Biomedical Implant Devices

This paper presents a power management concept for solar energy harvesting power management using an on-chip switched-capacitor (SC) DC-DC converter for biomedical implantable applications. This design eliminates potential reversion losses caused by the switching scheme. It also mitigates the bottom plate loss by employing the charge recycling technique. Moreover, instead of using a single step clock pulse, the two-step adiabatic charge sharing clock helps reduce the energy drawn from the PV cell by 65%. Furthermore, with the help of clock disabler scheme, the power dissipation has been further reduced by disabling the entire start-up charge pump once the desired reference output voltage was reached. However, due to additional circuitry for the clock disabler, there is a tradeoff between power efficiency and power dissipation. The proposed system was implemented and fabricated in a standard 0.18-µm TSMC RF CMOS technology. The proposed converter has achieved a maximum efficiency of 73%