290 research outputs found
Fast Software Polar Decoders
Among error-correcting codes, polar codes are the first to provably achieve
channel capacity with an explicit construction. In this work, we present
software implementations of a polar decoder that leverage the capabilities of
modern general-purpose processors to achieve an information throughput in
excess of 200 Mbps, a throughput well suited for software-defined-radio
applications. We also show that, for a similar error-correction performance,
the throughput of polar decoders both surpasses that of LDPC decoders targeting
general-purpose processors and is competitive with that of state-of-the-art
software LDPC decoders running on graphic processing units.Comment: 5 pages, 3 figures, submitted to ICASSP 201
VLSI Architectures for WIMAX Channel Decoders
This chapter describes the main architectures proposed in the literature to
implement the channel decoders required by the WiMax standard, namely
convolutional codes, turbo codes (both block and convolutional) and LDPC. Then
it shows a complete design of a convolutional turbo code encoder/decoder system
for WiMax.Comment: To appear in the book "WIMAX, New Developments", M. Upena, D. Dalal,
Y. Kosta (Ed.), ISBN978-953-7619-53-
Research on energy-efficient VLSI decoder for LDPC code
制度:新 ; 報告番号:甲3742号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6113Waseda Universit
The implementation of an LDPC decoder in a Network on Chip environment
The proposed project takes origin from a cooperation initiative named NEWCOM++ among
research groups to develop 3G wireless mobile system. This work, in particular, tries to focuse on
the communication errors arising on a message signal characterized by working under WiMAX
802.16e standard. It will be shown how this last wireless generation protocol needs a specific
flexible instrumentation and why an LDPC error correction code suitable in order to respect the
quality restrictions. A chapter will be dedicated to describe, not from a mathematical point of view,
the LDPC algorithm theory and how it can be graphically represented to better organize the
decodification process.
The main objective of this work is to validate the PHAL-concept when addressing a
complex and computationally intensive design like the LDPC encoder/decoder. The expected results
should be both conceptual; identifying the lacks on the PHAL concept when addressing a real
problem; and second to determine the overhead introduced by PHAL in the implementation of a
LDPC decoder.
The mission is to build a NoC (Network on Chip) able to perform the same task of a general
purpose processor, but in less time and with better efficiency, in terms of component flexibility and
throughput. The single element of the network is a basic processor element (PE) formed by the
union of two separated components: a special purpose processor ASIP, the responsible of the input
data LDPC decoding, and the router component PHAL, checking incoming data packets and
scanning the temporization of tasks execution.
Supported by a specific programming tool, the ASIP has been completely designed, from the
architecture resources to the instruction set, through a language like C. Realized in this SystemC
code and converted in VHDL language, it's been synthesized as to fit onto an FPGA of the Xilinx
Virtex-5 family. Although the main purpose regards the making of an application as flexible as
possible, a WiMAX-orientated LDPC implemented on a FPGA saves space and resources, choosing
the one that best suits the project synthesis. This is because encoders and decoders will have to find
room in the communication tools (e.g. modems) as best as possible.
The whole network scenary has been mounted through a Linux application, acting as a
master element. The entire environment will require the use of VPI libraries and components able to
manage the communication protocols and interfacing mechanisms
NanoMagnetic Logic Microprocessor Hierarchical Power Model
The interest on emerging nanotechnologies has been recently focused on NanoMagnetic Logic (NML), which has unique appealing features. NML circuits have a very low power consumption and, due to their magnetic nature, they maintain the information safely stored even without power supply. The nature of these circuits is highly different from the CMOS ones. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics 3) modeling performance aspects like speed and power, together with logic behavior. In this contribution we present a VHDL behavioral model for NML circuits, which allows to evaluate not only logic behavior but also power dissipation. It is based on a technological solution called ``snake-clock''. We demonstrate this model on a case study which offers the right variety of internal substructures to test the method: a four bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area and power dissipation, which we evaluated using as benchmark a division algorithm. Results highlight the flexibility and the efficiency of this model, and the remarkable improvements that it brings to the analysis of NML circuit
Ultra-low power LDPC decoder design with high parallelism for wireless communication system
制度:新 ; 報告番号:甲3423号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures
Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network- on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based desig
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